Multi-chip module

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Insulating material

Reexamination Certificate

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C257S706000, C257S704000, C257S712000, C257S713000, C257S717000, C257S720000, C257S723000, C361S704000, C361S705000, C361S716000, C361S715000

Reexamination Certificate

active

06281575

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a multi-chip module having a plurality of semiconductor integrated circuit elements (e.g. IC chips) and a cooling member soldered on the semiconductor integrated circuit elements.
As operation frequencies of semiconductor integrated circuit elements speed up, the heat generated from such semiconductor integrated circuit elements increases corresponding to a greater extent. The heat from such semiconductor integrated circuit elements can be reduced with air-cooling methods, air-blast cooling methods, and water-cooling methods. One of these cooling systems is selected appropriately to the heat value of the semiconductor integrated circuit elements. However, even water-cooling systems, which are the best in cooling performance, require higher efficiency of heat transmission between the back side of each of the semiconductor integrated circuit elements and the water-cooling member.
Higher efficiency heat transfer methods, such as the comb-teeth method, the heat transfer grease or the adhesive heat transfer method, and the solder-fixing method, are now under investigation. Among these heat transfer methods, the solder-fixing method with a higher heat transfer rate, which uses a low fusion point metal, is the highest cooling efficiency method. Such solder-fixing methods are disclosed in, for example, U.S. Pat. No. 5,325,265, Unexamined Published Japanese Patent Application Nos. Sho 60-253248, Sho 54-78982, Hei 6-77361, Hei 6-21278, and Hei 5-160306.
However, semiconductor integrated circuit elements, a substrate on which those semiconductor integrated circuit elements are mounted, and a cooling member have warping, uneven thickness, and roughness. Consequently, a solder-fixing method used with a multi-chip module causes a variability of solder thickness among solder portions which are soldered between the semiconductor integrated circuit elements and the cooling member.
In order to eliminate this variability, the following two methods have been considered: (1) to provide a proper amount of solder according to the necessary thickness at every soldered portion; and (2) to provide a fixed amount of solder and to dispose of surplus solder at every soldered portion.
In case of the method (1), an additional process is required to measure the thickness of solder at each soldered portion. Consequently, this method makes processing more complicated.
In case of the method (2), this method doesn't need to measure the thickness of the solder Technologies for disposing of surplus solder are disclosed in the Unexamined Published Japanese Patent Applications Nos. Sho 54-78982, Hei 6-21278, and Hei 5-160306. Especially, these documents disclose technology for simplifying the process of disposing of surplus solder. According to these technologies, a hole is formed corresponding to each of heat generating parts for disposing of surplus solder. The cooling member is soldered fixedly at the back side of heat generating parts such as semiconductor integrated circuit elements. In this case, solder is injected into the hole for filling and connecting the portions between the heat generating part and the cooling member with solder. Besides, if the surplus solder occurs, the surplus solder is disposed of by this hole for eliminating the variability of solder thickness at each soldered portion.
The above conventional technologies can dispose of surplus solder generated by a variability of solder thickness at soldered portions. But these technologies have the following problems.
In these technologies, the surplus solder is filled into a hole at each soldered portion. The amounts of filled surplus solder are each of the soldering portions are different from each other. Consequently, the positions of the solder surfaces in those holes are different from each other. As shown in the Unexamined Published Japanese Patent Nos. Sho 54-78982 and Hei 5-160306, those conventional technologies are still effective just as in the case of dealing with a low heat generation, such as using an air-cooling method.
But in case of dealing with a high test generation such as using a water-cooling method, some arrangements for the effective heat transfer from different heights of the solder surface in the holes are required. For example, in the Unexamined Published Japanese Patent Application No. Hei 6-21278, a low viscosity heat transfer material is disposed between a heat transfer plate which includes holes for filling and disposing solder and a cooling structure in which cooling water flows so as to make them in contact with each other for transferring the heat effectively, e.g., a heat transfer plate.
BRIEF SUMMARY OF THE INVENTION
Now that semiconductor integrated circuit elements generate high heat more and more, it is strongly required that those semiconductor integrated circuit elements are structured so as to cool down more effectively. Especially, a structure that a cooling member is soldered directly at the back side of each of those semiconductor integrated circuit elements is required. In such a case, however, it is difficult for the conventional technologies to manufacture structure with holes to eliminate the variability of solder thickness.
Under such the circumstances, it is an object of the present invention to provide a structure for eliminating much more surplus solder at soldered portions. In this structure, a cooling member is soldered directly at the back side of a heat generating member such as a semiconductor integrated circuit element.
It is another object of the present invention to provide a structure for providing uniform temperature distribution caused by the uneven heat generation from the semiconductor integrated circuit elements.
In order to achieve the above objects, the present invention has a structure that a metallized part A formed at a cooling member is larger than a metallized part B formed at the back side of semiconductor integrated circuit element which us soldered with the first metallized part.
The size of metallized part A is different from the size of metallized part B. Consequently, this structure has an area where the metallized part does not overlap the metallized part A. As the surplus solder occurs at the soldered portion between the metallized part A and the metallized part B, the surplus solder is pushed out to the area and some amount of the surplus solder is disposed out of the area. Besides, the amount of the surplus solder can be controlled by the area size.
In addition, the present invention has a structure that a center of metallized part A formed at a cooling member is shifted from a center of metallized part B formed at the back side of a semiconductor integrated circuit element which is soldered with the metallized part A.
By shifting the center of metallized part A or metallized part B, it is possible to increase the area size where the metallized part B does not overlap the metallized part A. Consequently according to this increase, it is also possible to increase the amount of the allowable surplus solder efficiently at each soldered portion.
And, furthermore, the present invention has a structure that the center of metallized part A is shifted from the center of metallized part B so that the solder width might become wider at the high heat generating area of the semiconductor integrated circuit element than at the low heat generating area. Consequently, it is possible to make the temperature distribution of the semiconductor integrated circuit element uniform by expanding the solder width at the high heat generation area side of the semiconductor integrated circuit element. As a result, the temperature distribution caused by uneven heat generation from the semiconductor integrated circuit elements can be made uniform.
The above structure is suitable for use in multi-chip modules and computers.


REFERENCES:
patent: 4034468 (1977-07-01), Koopman
patent: 5325265 (1994-06-01), Turlik et al.
patent: 54-78982 (1979-06-01), None
patent: 60-253248 (1985-12-01), None
patent: 5-160306 (1993-06-01), None

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