Multi-chip memory devices and modules including independent...

Details Multi-chip memory devices and modules including independent... Multi-chip memory devices and modules including independent...

2001-08-01

2004-07-27

Nelms, David (Department: 2818)

Static information storage and retrieval

Format or disposition of elements

C365S063000, C257S787000, C257S203000, C438S112000, C438S124000

Reexamination Certificate

active

06768660

ABSTRACT:

RELATED APPLICATION
This application claims the benefit of Korean Patent Application No. 2001-1019, filed Jan. 8, 2001, the disclosure of which is hereby incorporated herein by reference in its entirety as if set forth fully herein.
FIELD OF THE INVENTION
The present invention relates to memory devices, and more particularly to multi-chip memory devices that include at least two chips in one package, memory modules including the multi-chip memory devices, and control methods for the multi-chip memory devices and memory modules.
BACKGROUND OF THE INVENTION
Integrated circuit memory chips are widely used in consumer and commercial applications. In these applications, it may be desirable to increase the amount of memory that can be packaged in a given area or volume. Accordingly, multi-chip memory devices have been used, wherein at least two integrated circuit memory chips are encapsulated in a common package that includes a plurality of external terminals. It is also known to mount a plurality of multi-chip memory devices on first and second opposing surfaces of a memory module substrate, to provide a memory module.
For example, a 144-pin/200-pin memory module mounted on a main board of a notebook computer can include a small outline dual in-line memory module (SODIMM) having a width of 1.25 inches, a height of 2.66 inches and a thickness of 0.15 inches and a micro-dual in-line memory module (&mgr;-DIMM) having a width of 1.18 inches, a height of 1.5 inches and a thickness of 0.15 inches. The size of the memory module is determined in accordance with the joint electronic devices engineering council (JEDEC) standard. On such a memory module, up to four synchronous dynamic random access memory (SDRAM) of a 54-pin thin small outline package (TSOP) type can be mounted on both its front surface and its rear surface, respectively.
FIGS. 1A and 1B
are plan views illustrating, respectively, configurations of a front surface and a rear surface of a conventional 144-pin/200-pin memory module. As shown in
FIGS. 1A and 1B
, the front surface
10
of the module includes four memory devices
12
-
1
to
12
-
4
, and the rear surface
20
also includes four memory devices
22
-
1
to
22
-
4
. On both the front and rear surfaces
10
and
20
of the memory module, signal lines are arranged to connect the memory devices
12
-
1
to
12
-
4
and
221
to
22
-
4
with connecting pins
14
-
1
,
14
-
2
,
24
-
1
, and
24
-
2
. The connecting pins
14
-
1
and
14
-
2
of the front surface
10
and the connecting pins
24
-
1
and
24
-
2
of the rear surface
20
are connected with signal lines of a main board or motherboard through slots of the main board. A pin configuration of the memory module includes 12 input pins, 2 bank selecting signal pins, 64 data input/output pins, one row address strobe pin, one column address strobe pin, one write enable signal pin, 8 data input/output mask pins, and a predetermined number of no-connection pins.
FIG. 2
is a cross-sectional view of an SDRAM of the TSOP type for mounting on the module shown in FIG.
1
. As shown in
FIG. 2
, the memory device includes an encapsulating package
30
, a chip
32
, lead frames
34
-
1
and
34
-
2
, pads
361
and
36
-
2
, insulating materials
38
-
1
and
38
-
2
, and bonding wires
40
-
1
and
40
-
2
. The chip
32
and the lead frames
34
-
1
and
34
-
2
are respectively insulated by the insulating materials
38
-
1
and
38
-
2
, and the lead frames
34
-
1
and
34
-
2
and the pads
36
-
1
and
362
are respectively connected with each other via the bonding wires
40
-
1
and
40
-
2
. The lead frames
34
-
1
and
34
-
2
are used as signal input/output pins.
FIG. 3
is a plan view illustrating a pin configuration of an SDRAM of the 54-pin TSOP type. Pin numbers
1
,
14
and
27
denote a power supply (VDD) pin. Pin numbers
28
,
41
and
54
denote a power supply ground pin. Pin numbers
3
,
9
,
43
and
49
denote data output power pins. Pin numbers
6
,
12
,
46
and
52
denote data output power ground pins. Pin number
16
denotes a write enable signal (WEB) applying pin. Pin number
17
denotes a column address strobe signal (CASB) applying pin. Pin number
18
denotes a row address strobe signal (CASB) applying pin. Pin number
19
denotes a chip select signal (CSB) applying pin. Pin numbers
20
and
21
denote bank select address (BA
0
, BA
1
) applying pins. Pin numbers
22
to
26
and
29
to
36
denote address (A
0
to A
12
) applying pins. Pin number
37
denotes a clock enable signal (CKE) applying pin. Pin number
38
denotes a system clock signal (CLK) applying pin. Pin numbers
15
and
39
denote data input/output mask signal (LDQM, UDQM) applying pins. Pin numbers
2
,
4
,
5
,
7
,
8
,
10
,
11
,
13
,
42
,
44
,
45
,
47
,
48
,
50
,
51
and
53
denote data chip/output signal (DQ
0
to DQ
15
) pins. Pin number
40
denotes a no-connection pin.
A chip select signal (CSB) applied to the chip select signal (CSB) applying pin enables inputting of signals inputted to all the pins described above except the system clock signal (CLK) applying pin, the clock enable signal (CKE) applying pin and the data input/output mask signal (LDQM, UDQM) applying pins, so that an operation of the memory device is enabled. The system clock signal (CLK) applying pin is a pin for inputting the clock signal applied from a controller of the main board. Particularly, the clock enable signal (CKE) applying pin may be used as a control signal applying pin for a power-down mode of the notebook computer.
FIG. 4
is a plan view illustrating the memory devices mounted on the memory module of FIG.
1
and control signal lines. The memory module of
FIG. 4
is 256M byte memory module on which eight memory devices
12
-
1
to
12
-
4
and
22
-
1
to
22
-
4
of 16M×16 bits are mounted. In
FIGS. 1 and 4
, like reference numerals denote like parts.
The memory devices
12
-
1
to
12
-
4
arranged in a dotted line portion
10
′ are the memory devices mounted on the front surface
10
of the memory module. An operation of the memory devices
12
-
1
to
12
-
4
is enabled in response to the chip select signal (CSB
0
), and the system clock signal (CLK
0
) is enabled in response to the clock enable signal (CKE
0
), so that data is input or output in response to the system clock signal (CLK
0
). Data of 16 bits is input into or output from each of the memory devices
12
-
1
to
12
-
4
, and therefore the total data input into or output from the memory devices
12
-
1
to
12
-
4
is 64 bits.
The memory devices
22
-
1
to
22
-
4
arranged in a dotted line portion
20
′ are the memory devices mounted on the rear surface
20
of the memory module. An operation of the memory devices
22
-
1
to
22
-
4
is enabled in response to the chip select signal (CSB
1
), and the system clock signal (CLK
1
) is enabled in response to the clock enable signal (CKE
1
), so that data is input or output in response to the system clock signal (CLK
1
). Data of 16 bits is input into or output from each of the memory devices
22
-
1
to
22
-
4
, and therefore the total data input into or output from the memory devices
22
-
1
to
22
-
4
is 64 bits.
Other signal lines, which are not shown in
FIG. 4
, are connected to each other via common signal lines. That is, as shown in
FIG. 4
, in the 256M byte memory module, four memory devices of 16M×16 bits are respectively mounted on both its front surface
10
and its rear surface
20
. The four memory devices arranged on the front surface
10
and the four memory devices arranged on rear surface
20
can be operated independent from each other in order to input/output data of 64 bits into/from the 256M byte memory module. As shown in
FIG. 4
, in case the four memory devices mounted on the front and rear surfaces
10
and
20
are separately operated, in order to increase a capacity of the memory module, it may be desirable to increase the capacity of the memory devices. For example, in order to configure a 512M byte memory module, four memory devices of 16M

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