Multi-chip memory device with stacked memory chips, method...

Details Multi-chip memory device with stacked memory chips, method... Multi-chip memory device with stacked memory chips, method...

2008-09-26

2010-11-09

Tran, Michael T (Department: 2827)

Static information storage and retrieval

Format or disposition of elements

C365S063000

Reexamination Certificate

active

07830692

ABSTRACT:
A multi-chip memory device includes a transfer memory chip communicating input/output signals, a stacked plurality of memory chips each including a memory array having a designated bank, and a signal path extending upward from the transfer memory chip through the stack of memory chips to communicate input/output signals, wherein each bank of each memory chip in the stacked plurality of memory chips is commonly addressed to provide read data during a read operation and receive write data during a write operation, and vertically aligned within the stacked plurality of memory chips.

REFERENCES:
patent: 7330368 (2008-02-01), Saito et al.
patent: 7466577 (2008-12-01), Sekiguchi et al.
patent: 2004327474 (2004-11-01), None
patent: 2006012337 (2006-01-01), None
patent: 2006013337 (2006-01-01), None
patent: 2006277870 (2006-10-01), None

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