Multi-chip integrated circuit package structure for central...

Details Multi-chip integrated circuit package structure for central... Multi-chip integrated circuit package structure for central...

2000-03-14

2001-07-24

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With structure for mounting semiconductor chip to lead frame

66, 66, 66, 66, 66, C361S813000

Reexamination Certificate

active

06265763

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit (IC) packages, and more particularly, to a multi-chip IC package structure, which can be used to pack more than one IC chip therein and whose characterized structure allows a short bonding wire length so as to retain IC performance and save manufacture cost.
2. Description of Related Art
A multi-chip IC package is a type of IC package that is designed to enclose more than one IC chip therein, which can offer a manifold level of functionality than a single-chip IC package. Conventionally, there are many ways to pack more than one IC chip in a single package.
FIGS. 1A-1C
are schematic sectional diagrams used to depict three different types of multi-chip IC package structures.
FIG. 1A
shows a stacked type that packs two IC chips
11
a
,
12
a
, in a stacked manner;
FIG. 1B
shows a juxtaposed type that packs two IC chips
21
a
,
22
a
by arranging them side by side on the same lead frame plane; and
FIG. 1C
shows a back-to-back type that arranges two IC chips
31
a
,
32
a
in a back-to-back manner.
One drawback to the forgoing types of multi-chip IC package structures, however, is that they are only suitable for use to pack IC chips of peripheral-pad type, but unsuitable for use to pack IC chips of central-pad type (in this specification, the term “central-pad IC chip”refers to an IC chip whose bonding pads are arranged in the center thereof, whereas the term “peripheral-pad IC chip” refers to an IC chip whose bonding pads are arranged near the peripheral edge thereof. This is because that if the multi-chip IC package structures of
FIGS. 1A-1C
are used to pack IC chips of central-pad type, it would require an increase in the bonding wire length, thus undesirably degrading the IC performance and increasing the manufacture cost. This drawback is illustratively depicted in
FIGS. 2A-2C
.
As shown in
FIG. 2A
, if the package structure of
FIG. 1A
is used to pack a peripheral-pad IC chip
11
b
and a central-pad IC chip
12
b
, then it requires the use of a set of bonding wires
13
b
of a greater length than the bonding wires
13
a
for the peripheral-pad IC chip
12
a
shown in FIG.
1
A. As a consequence, it would degrade the IC performance and increase the overall manufacture cost.
As shown in
FIG. 2B
, if the package structure of
FIG. 1B
is used to pack two central-pad IC chips
21
b
,
22
b
, it requires the use of two sets of bonding wires
23
b
,
24
b
of a greater length than the bonding wires
23
a
,
24
a
for the peripheral-pad IC chip
21
a
,
22
a
shown in FIG.
1
B. As a consequence, it would degrade the IC performance and increase the overall manufacture cost.
As further shown in
FIG. 2C
, if the package structure of
FIG. 1C
is used to pack two central-pad IC chips
31
b
,
32
b
, it requires the use of two sets of bonding wires
33
b
,
34
b
of a greater length than the bonding wires
33
a
,
34
a
for the peripheral-pad IC chips
31
a
,
32
a
shown in FIG.
1
C. As a consequence, it would degrade the IC performance and increase the overall manufacture cost
SUMMARY OF THE INVENTION
It is therefore an objective of this invention to provide a multi-chip IC package, which can be used to pack more than one IC chip.
It is another objective of this invention to provide a multi-chip IC package, which allows the use of a short bonding wire length so as to retain IC performance and save manufacture cost.
In accordance with the foregoing and other objectives, the invention proposes a new multi-chip IC package. The multi-chip IC package structure of the invention includes the following constituent parts: (a) a lead frame having a central die pad, a first lead portion separated from the central die pad by a first gap, and a second lead portion separated from the central die pad by a second gap, (b) a first central-pad IC chip having a plurality of central pads located on the circuit surface thereof; the central pads dividing the circuit surface of the first central-pad IC chip into a first region and a second region, wherein the first region is attached to the back side of the first lead portion of the lead frame while the second region is attached to the back side of the central die pad of the lead frame, with the central pads on the first central-pad IC chip being aligned with the first gap between the central die pad and the first lead portion of the lead frame; (c) a second central-pad IC chip having a plurality of central pads located on the circuit surface thereof; the central pads dividing the circuit surface of the second central-pad IC chip into a first region and a second region, wherein the first region is attached to the back side of the second lead portion of the lead frame while the second region is attached to the back side of the central die pad of the lead frame, with the central pads on the second central-pad IC chip being aligned with the second gap between the central die pad and the second lead portion of the lead frame; (d) a peripheral-pad IC chip having a plurality of peripheral pads located on the circuit surface thereof, and the noncircuit surface of the peripheral-pad IC chip being attached to the front side of the central die pad of the lead frame; (e) a first set of bonding wires for electrically connecting the central pads on the first central-pad IC chip to the front side of the first lead portion of the lead frame; (f) a second set of bonding wires for electrically connecting the central pads on the second central-pad IC chip to the front side of the second lead portion of the lead frame; (g) a third set of bonding wires for electrically connecting the peripheral pads on the peripheral-pad IC chip to the front side of the first and second lead portions of the lead frame; and (h) an encapsulant for encapsulating the first central-pad IC chip, the second central-pad IC chip, and the peripheral-pad IC chip.
The foregoing multi-chip IC package of the invention can be used to pack two central-pad IC chips and one peripheral-pad IC chip, while nevertheless allowing the bonding wires applied to the two central-pad IC chips to be short in length so as to retain IC performance and save manufacture cost. The multi-chip IC package of the invention is therefore more advantageous to use than the prior art.


REFERENCES:
patent: 5012323 (1991-04-01), Farnworth
patent: 5646829 (1997-07-01), Sota
patent: 5793108 (1998-08-01), Nakanishi et al.
patent: 5898220 (1999-04-01), Ball
patent: 404179264 (1992-06-01), None

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