Multi-chip device and method of fabrication employing leads over

Details Multi-chip device and method of fabrication employing leads over Multi-chip device and method of fabrication employing leads over

1995-12-19

1997-11-18

Thomas, Tom

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With structure for mounting semiconductor chip to lead frame

257690, 257724, 437207, 437220, H01L 23495, H01L 2334

Patent

active

056891350

ABSTRACT:
A device and method for increasing integrated circuit density comprising a pair of superimposed dies with a plurality of leads extending between the dies. The device is produced by providing a lower die which has a plurality of bond pads on a face side of the lower die. A layer of dielectric or insulative shielding is applied over the lower die face side. Leads are applied to an upper surface of the shielding layer. A plurality of lower die bond wires is attached between the lower die bond pads and an upper surface of their respective leads. A second layer of dielectric or insulative shielding is applied over the leads and the portion of the lower die bond wires extending over the lead upper surfaces. A back side of the upper die is adhered to an upper surface of the second shielding layer. A plurality of upper die bond wires are attached between a plurality of bond pads on a face side of the upper die and the upper surface of their respective leads.

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patent: 5101324 (1992-03-01), Sato
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patent: 5463253 (1995-10-01), Waki et al.
patent: 5471369 (1995-11-01), Honda et al.
patent: 5479051 (1995-12-01), Waki et al.
patent: 5523608 (1996-06-01), Kitaoka et al.
patent: 5539250 (1996-07-01), Kitano et al.
patent: 5579208 (1996-11-01), Honda et al.

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