Multi-chip addressing for the I2C bus

Details Multi-chip addressing for the I2C bus Multi-chip addressing for the I2C bus

1999-12-13

2003-09-30

Auve, Glenn A. (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

System configuring

Reexamination Certificate

active

06629172

ABSTRACT:

BACKGROUND OF THE INVENTION
In modern electronic systems there are a number of peripheral integrated circuits (ICs) that need to communicate with each other and with off-chip element. To maximize hardware efficiency and simplify circuit design, a simple bi-directional 2-wire, serial data (SDA) and serial clock (SCL) bus for inter-IC control (I
2
C) was developed. This I
2
C-bus supports any IC fabrication process and, with the extremely broad range of I
2
C-compatible chips, it has become the worldwide industry standard proprietary control bus.
Each device on the I
2
C-bus is recognized by a unique address and can operate as either a receiver-only device (e.g. an LCD Driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. An I
2
C-bus is a multi-master bus, i.e. it can be controlled by more than one IC connected to it.
Devices on the I
2
C bus are selected by an 8-bit address which is sent over the bus in the same way as data bytes. The least significant bit of this address acts as a read/write control signal, and is set to 0 to make the Slave a Receiver and 1 to make the Slave a Transmitter.
The address byte is the first byte transmitted after a Start condition, and is always transmitted by the Master. By convention, if the Slave is a Receiver and the Slave contains several registers, then the next byte transmitted after the address is an internal register address for the device. However, this is not required by the I
2
C specification.
The address of a particular slave device is often determined when the I
2
C is manufactured. If there is more than one device with the same address on the I
2
C bus, it is difficult to access each device individually.
Therefore, each device.coupled to a system management bus based on the I
2
C protocol is required to have its own I
2
C address for proper operation of the bus. The current method for assigning addresses to agents on the bus is for the designer to provide a hard wired solution or provide dip switches or jumpers. Although hard address bits assigns every device to a unique address, this approach requires extra pads and requires the maximum number of devices capable of being attached to the bus to be determined upon fabrication. When the designer provides dip switches or jumpers, the user is required to either manually set the dip switches or jumpers or use configuration software to operate logical switches. This requirement to manually set switches or to operate switches through software can be both tedious and error prone. Therefore a system and method is desired for assigning unique addresses to devices on an I
2
C bus in a computer system after the devices are connected to the bus.
SUMMARY OF THE INVENTION
The present invention describes a system for automatically assigning unique addresses to multiple devices attached to an I
2
C bus. When multiple devices share the same I
2
C address, the master device is unable to communicate with each device individually. Therefore, a circuit enable input is created to individually activate each device sharing a common address. Once a device is activated, the master device may communicate to the device a unique I
2
C bus address, after which the activated device only responds to the new address. Each device initially sharing the same address is activated individually until all devices have been assigned a unique address.
One aspect of the present invention is a method of assigning addresses to a plurality of devices connected to a system management bus. The method comprises the steps of enabling a first of the plurality of devices and communicating a first address to the first of the plurality of devices. The method also includes the steps of indicating the first address is received by the first of the plurality of devices and enabling a second of the plurality of devices. A second address is communicated to the second of the plurality of devices. The method may further comprise the steps of indicating the second address is received by the second of the plurality of devices and then determining if additional devices are present. If additional devices are present, the method then enables a third of the plurality of and communicates a third address to the third of the plurality of devices.
Another aspect of the present invention is a system for assigning addresses on a bus having a data line. The system comprises a plurality of devices connected to the data line of the bus. Each of the devices has an enable input and an enable next output. The devices are connected so the enable next output of a first device is coupled to the enable input of a second device. A start signal is coupled to the enable input of the first device. When the start input is high, the first device communicates with the data line on the bus to receive a first address. The enable next output of the first device is then set high.


REFERENCES:
patent: 5204669 (1993-04-01), Dorfe et al.
patent: 5636342 (1997-06-01), Jeffries
patent: 5974475 (1999-10-01), Day et al.
patent: 6009479 (1999-12-01), Jeffries
patent: 6026354 (2000-02-01), Singh et al.
patent: 6363437 (2002-03-01), Ptasinski et al.

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