Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral adapting
Reexamination Certificate
2007-09-18
2007-09-18
Padmanabhan, Mano (Department: 2181)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral adapting
C710S001000, C710S062000, C710S065000
Reexamination Certificate
active
10637982
ABSTRACT:
A serial interface for a programmable logic device substantially eliminates skew across multiple channels both in the receiver and in the transmitter. Even when the channels are independent (e.g., are in different quads), skew is substantially eliminated by monitoring to determine when all channels have reached their active states (i.e., in the case of receiver channels when all channels have achieved byte alignment and have received an alignment character, and in the case of transmitter channels when all transmit PLLs have locked), and only then allowing data to flow between the serial and parallel domains.
REFERENCES:
patent: 3473160 (1969-10-01), Wahlstrom
patent: 4486739 (1984-12-01), Franaszek et al.
patent: 5689195 (1997-11-01), Cliff et al.
patent: 5802103 (1998-09-01), Jeong
patent: 5909126 (1999-06-01), Cliff et al.
patent: 6031428 (2000-02-01), Hill
patent: 6215326 (2001-04-01), Jefferson et al.
patent: 6240471 (2001-05-01), Schlueter et al.
patent: 6270350 (2001-08-01), Christopher
patent: 6370603 (2002-04-01), Silverman
patent: 6388591 (2002-05-01), Ng
patent: 6407576 (2002-06-01), Ngai et al.
patent: 6512804 (2003-01-01), Johnson et al.
patent: 6618395 (2003-09-01), Kimmitt
patent: 2001/0033188 (2001-10-01), Aung et al.
patent: 2002/0190751 (2002-12-01), Lee et al.
patent: 2003/0052709 (2003-03-01), Venkata et al.
patent: 2003/0155955 (2003-08-01), Andrasic et al.
Agere Systems, Inc.; “ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface FPSC;” Jul. 2001; Preliminary Data Sheet; pp. 1-35.
Victor P. Nelson et al.; Digital Logic Circuit Analysis & Design; 1995; Prentice-Hall, Inc.; pp. 131-132.
Agere Systems, Inc., “ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface FPSC,” Preliminary Data Sheet, pp. 1-35 (Jul. 2001).
Agere Systems, Inc., “ORCA ORT8850 Field-Programmable System Chip (FPSC) Eight Channel x 850 Mbits/s Backplane Transceiver,” Product Brief, pp. 1-6 (Jul. 2001).
Agere Systems, Inc., “ORCA ORT8850 Field-Programmable System Chip (FPSC) Eight Channel x 850 Mbits/s Backplane Transceiver,” Product Brief, pp. 1-36 (Aug. 2001).
Cook, Barry M., “IEEE 1355 Data-Strobe Links: ATM Speed at RS232 Cost,”Microprocessors and Microsystems, vol. 21, No. 7-8, pp. 421-428 (Mar. 30, 1998).
Electronic Trend Publications, Inc., “Lucent Introduces 10Gb/s Ethernet FPGAs,”Programmable LogicNews and Views, vol. 9, No. 11, pp. 7-8 (Nov. 2000).
Konstas, Jason, “Converting Wide, Parallel Data Buses to High Speed Serial Links,”International IC '99 Conference Proceedings, pp. 19-30 (1991).
Lucent Technologies, Inc., “Protocol Independent Gigabit Backplane Transceiver Using Lucent ORT4622/ORT8850 FPSCs,” Application Note, pp. 1-10 (Jun. 2000).
Lucent Technologies, Inc., “ORCA ORT82G5 0.622/1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface FPSC,” Product Brief, pp. 1-8 (Feb. 2001).
Xilinx, Inc.,Virtex-II Pro Platform FPGA Handbook(UG012 Version 1.0), pp. 1-6, 27-32, 121-126, and 162-180 (Jan. 31, 2002).
Xilinx, Inc., Rocket I/O Transceiver User Guide (UG024 Version 1.2), pp. 1-106 (Feb. 25, 2002).
Lee Chong H
Patel Rakesh
Venkata Ramanand
Altera Corporation
Franklin, Jr. Richard B.
Ingerman Jeffrey H.
Padmanabhan Mano
Ropes & Gray LLP
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