Multi-channel integrity checking data transfer system for contro

Details Multi-channel integrity checking data transfer system for contro Multi-channel integrity checking data transfer system for contro

1994-08-15

1996-05-14

Beausoliel, Jr., Robert W.

Excavating

371 3, 371 471, G06F 1300, G06F 1100

Patent

active

055176151

ABSTRACT:
A buffer memory holding blocks of data received from a main host computer has dedicated portions for data destined for different sets of sender-receiver units. Each sender-receiver unit has a channel bus path to the buffer memory and each channel bus is monitored by an on-the-fly integrity checking circuit.
A control processor and associated bus arbitration logic provide signals to a multiplexer so as to allocate equal access periods to each channel bus for connection to the buffer memory. A data feeder control on each transfer channel senses the availability of data block words in each dedicated segment of the buffer memory so that partial transfers of word blocks may occur on minor cycles with subsequent completion of the blocks of data words on a major transfer cycle.

REFERENCES:
patent: 3582906 (1971-06-01), Beausoliel et al.
patent: 4327408 (1982-04-01), Frissell et al.
patent: 4542457 (1985-09-01), Mortensen et al.
patent: 5291496 (1994-03-01), Andaleon et al.
patent: 5377328 (1994-12-01), Benham
patent: 5428766 (1995-06-01), Seaman

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