Multi-channel flash module with plane-interleaved sequential...

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique

Reexamination Certificate

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C711S103000

Reexamination Certificate

active

07966462

ABSTRACT:
A RAM mapping table is restored from flash memory using plane, block, and page addresses generated by a physical sequential address counter. The RAM mapping table is restored following a plane-interleaved sequence generated by the physical sequential address counter using interleaved bits extracted from the lowest bits of the logical block index. These plane-interleave bits are split into a LSB and a MSB, with middle physical block bits between the LSB and MSB. The physical sequential address counter generates a physical block number by incrementing the plane-interleave bits before the middle physical block bits, and then relocating the MSB to above the middle physical block bits. This causes blocks to be accessed in a low-high sequence of0, 1, 4096, 4097, 2, 3, 4098, 4099, etc. in the four planes of flash memory. Background recycling and ECC writes are also performed.

REFERENCES:
patent: 6571326 (2003-05-01), Spiegel et al.
patent: 6725321 (2004-04-01), Sinclair et al.
patent: 2002/0194451 (2002-12-01), Mukaida et al.
patent: 2006/0156078 (2006-07-01), Baumhof et al.

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