Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2000-06-09
2004-02-03
Bataille, Pierre Michel (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S118000, C710S022000, C710S039000, C710S038000
Reexamination Certificate
active
06687796
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention generally relates to microprocessors, and more specifically to improvements in direct memory access circuits, systems, and methods of making.
BACKGROUND OF THE INVENTION
Microprocessors are general purpose processors which provide high instruction throughputs in order to execute software running thereon, and can have a wide range of processing requirements depending on the particular software applications involved. A direct memory access (DMA) controller is often associated with a processor in order to take over the burden of transferring blocks of data from one memory or peripheral resource to another and to thereby improve the performance of the processor.
Many different types of processors are known, of which microprocessors are but one example. For example, Digital Signal Processors (DSPs) are widely used, in particular for specific applications, such as mobile processing applications. DSPs are typically configured to optimize the performance of the applications concerned and to achieve this they employ more specialized execution units and instruction sets. Particularly in applications such as mobile telecommunications, but not exclusively, it is desirable to provide ever increasing DSP performance while keeping power consumption as low as possible.
SUMMARY OF THE INVENTION
Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Combinations of features from the dependent claims may be combined with features of the independent claims as appropriate and not merely as explicitly set out in the claims. The present invention is directed to improving the performance of digital systems with processors, such as for example, but not exclusively, digital signal processors.
In accordance with a first aspect of the invention, there is provided a digital system with a plurality of requestor circuits each having at least one request address output node for providing a request address and at least one request output. A port circuit has a request address input node connected to the request address output nodes of the plurality of requestor circuits, a memory address output node for providing a memory address selected from the plurality of request address output nodes to a respective associated memory resource, and a scheduler circuit operable to select the next request that will be served by the port. The scheduler circuit comprises an allocation circuit with a plurality of request inputs each connected to a respective request output on the plurality of requester circuits, and a request output for providing a subset of request signals selected from the plurality of request inputs; and an interleaver circuit with a request input connected to the request output of the allocation circuit, the interleaver circuit operable to select the next request from among the subset of request signals that will be served next by the port circuit.
In accordance with another aspect of the present invention, the interleaver circuit comprises a request allocation table memory circuit connected to the request input and the allocation circuit is operable to store the subset of request signals in the request allocation table.
In accordance with another aspect of the present invention, the interleaver circuit has a number selector circuits which each have a control input connected to the request allocation table memory circuit. Each of the selector circuits has a plurality of status inputs connected to receive a status signal from each requestor circuit. Each selector circuit has an output to provide the selected status signal.
In accordance with another aspect of the present invention, a method of operating a digital system having a memory resource and a plurality of requestor circuits which each require access to the memory resource is provided. A subset of requests from the requestor circuits are allocated and stored in a request allocation table. The subset of requests from the request allocation table are interleaved to determine the next request that will be presented to the memory resource.
According to another aspect of the present invention, the step of interleaving includes evaluating a ready status of each request in the request allocation table and ignoring a request that is not ready.
According to another aspect of the present invention the step of allocating includes selecting the subset of requests from the plurality of requestor circuits based on a priority assigned to each requestor circuit. A request from a requestor is removed from the request allocation table if a request is received from a second requestor having a higher priority than the first requestor.
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Laine Armelle
Mazzocco Daniel
Ollivier Gerald
Six Laurent
Bataille Pierre Michel
Brady III W. James
Marshall, Jr. Robert D.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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