Multi bus access memory

Details Multi bus access memory Multi bus access memory

1997-12-17

2000-10-24

Bragdon, Reginald G.

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

711105, 711131, 711171, 711172, G06F 1316

Patent

active

061382043

ABSTRACT:
The present invention relates to memory and methods for storing/retrieving data in/from the memory that is accessed by at least two distinct data uses of different actual word widths. A memory for storing addressable binary data comprises a data storage organized in rows and columns of bit array cells, row address decoder and driver for addressing a selected row of bit array cells, column drivers for driving selected columns of bit array cells, and a bus switch port for selectively transferring data between the data storage and a first data bus with a first bus word width p and a second data bus with a second bus word width q smaller than the first bus word width p.

REFERENCES:
patent: 4633437 (1986-12-01), Mothersole et al.
patent: 4683534 (1987-07-01), Tietjen et al.
patent: 4751671 (1988-06-01), Babetski et al.
patent: 5426424 (1995-06-01), Vanden Heuvel et al.
patent: 5481496 (1996-01-01), Kobayashi et al.
patent: 5579484 (1996-11-01), Cooper
patent: 5893927 (1999-04-01), Hovis
English Abstract of German Patent No. dd 284323.

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