Multi bridge channel field effect transistors with nano-wire...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor

Reexamination Certificate

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C438S206000, C257SE21418, C257SE29257

Reexamination Certificate

active

07427788

ABSTRACT:
A field effect transistor (FET) includes spaced apart source and drain regions disposed on a substrate and at least one pair of elongate channel regions disposed on the substrate and extending in parallel between the source and drain regions. A gate insulating region surrounds the at least one pair of elongate channel regions, and a gate electrode surrounds the gate insulating region and the at least one pair of elongate channel regions. Support patterns may be interposed between the semiconductor substrate and the source and drain regions. The elongate channel regions may have sufficiently small cross-section to enable complete depletion thereof. For example, a width and a thickness of the elongate channel regions may be in a range from about 10 nanometers to about 20 nanometers. The elongate channel regions may have rounded cross-sections, e.g., each of the elongate channel regions may have an elliptical cross-section. The at least one pair of elongate channel regions may include a plurality of stacked pairs of elongate channel regions.

REFERENCES:
patent: 6709982 (2004-03-01), Buynoski et al.
patent: 6800910 (2004-10-01), Lin et al.
patent: 6970373 (2005-11-01), Datta et al.
patent: 06-140636 (1994-05-01), None
patent: 11-008390 (1999-01-01), None
patent: 1020020078996 (2002-10-01), None
Notice to Submit Response in Korean Application No. 10-2004-0086555; Date of mailing: May 18, 2006.
English translation of Notice to Submit Response in Korean Application No. 10-2004-0086555; Date of mailing May 18, 2006.

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