Multi-bit testing circuit for semiconductor memory device

Details Multi-bit testing circuit for semiconductor memory device Multi-bit testing circuit for semiconductor memory device

1995-01-25

1996-10-22

Nguyen, Viet Q.

Static information storage and retrieval

Read/write circuit

Testing

365196, 365205, 365200, G11C 2900, G11C 1120

Patent

active

055684343

ABSTRACT:
A multi-bit testing circuit for testing a semiconductor memory device having a plurality of memory cells. The multi-bit testing circuit includes a first amplifier which is coupled to a first group of memory cells and which senses a pair of bit line signals associated with a respective one of the memory cells of the first group and provides each of the sensed pair of bit line signals to a respective one of first and second output lines of a common signal path; a second amplifier which is coupled to a second group of memory cells and which senses a pair of bit line signals associated with a respective one of the memory cells of the second group and provides each of the sensed pair of bit line signals to a respective one of the first and second output lines of the common signal path; and a third amplifier which is coupled to the first and second output lines of the common signal path and which produces an output signal in response to the sensed pair of bit line signals provided on the first and second output lines.

REFERENCES:
patent: 5088063 (1992-02-01), Matsuda et al.
patent: 5184327 (1993-02-01), Matsuda et al.
"A 45-nc 64-Mb DRAM with a Merged Match-Line Test Architecture", Shigeru Mori et al., IEEE Journal of Solid-State Circuits, 11(26):1486-1491 (1991).
"A 21-mW 4-Mb CMOS SRAM for Battery Operation", Shoji Murakami et al., IEEE Journal of Solid-State Circuits, 11(26):1563-1568 (1991).

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