Multi-bit test circuit

Details Multi-bit test circuit Multi-bit test circuit

2005-02-08

2005-02-08

Lamarre, Guy J. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S048000, C365S201000

Reexamination Certificate

active

06854078

ABSTRACT:
Internal read out data bits are divided into a plurality of data groups, and data bits in corresponding positions in different data groups are paired off. A determination gate is provided to each pair of data bits, and determining operation is performed in each pair to compress the result of determination to finally generate a 1-bit flag indicating a match/mismatch in logic level among the internal read out data. Consequently, a multi-bit test circuit that has a reduced layout area and can perform high-speed multi-bit determination is provided.

REFERENCES:
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patent: 5706234 (1998-01-01), Pilch et al.
patent: 5838627 (1998-11-01), Tomishima et al.
patent: 6421794 (2002-07-01), Chen et al.
patent: 6484289 (2002-11-01), Hsu
patent: 5-211000 (1993-08-01), None
patent: 9-185899 (1997-07-01), None

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