Multi-bit non-volatile memory device and method therefor

Details Multi-bit non-volatile memory device and method therefor Multi-bit non-volatile memory device and method therefor

2005-02-15

2005-02-15

Chaudhari, Chandra (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S324000

Reexamination Certificate

active

06855979

ABSTRACT:
A multi-bit non-volatile memory device includes a charge storage layer (14) sandwiched between two insulating layers (12and16) formed on a semiconductor substrate (10). A thick oxide layer (18) is formed over the charge storage layer (14) and a minimum feature sized hole is etched in the thick oxide layer (18). An opening is formed in the thick oxide layer (18). Side-wall spacers (60) formed on the inside wall of the hole over the charge storage layer have a void (62) between them that is less than the minimum feature size. The side-wall spacers (60) function to mask portions of the charge storage layer (14), when the charge storage layer is etched away, to form the two separate charge storage regions (55and57) under the side-wall spacers (60). The device can be manufactured using only one mask step. Separating the charge storage regions prevents lateral conduction of charge in the nitride.

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Lusky et al., “Electrons Retention Model for Localized Charge in Oxide-Nitride-Oxide (ONO) Dielectric,” IEEE Electron Device Letters, vol. 23, No. 9, Sep. 2002, pp. 556-558.

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