Multi-bit flash memory devices and methods of programming...

Static information storage and retrieval – Floating gate – Multiple values

Reexamination Certificate

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C365S185330, C365S185180

Reexamination Certificate

active

08072804

ABSTRACT:
A non-volatile memory device includes an array of non-volatile memory cells configured to support single bit and multi-bit programming states. A control circuit is provided, which is configured to program a first page of non-volatile memory cells in the array as M-bit cells during a first programming operation and further configured to program the first page of non-volatile memory cells as N-bit cells during a second programming operation. The first and second programming operations are separated in time by at least one operation to erase the first page of non-volatile memory cells. M and N are unequal integers greater than zero.

REFERENCES:
patent: 7180775 (2007-02-01), Meir
patent: 7518914 (2009-04-01), Han
patent: 2007/0274128 (2007-11-01), Kamei
patent: 2008/0055985 (2008-03-01), Kanda
patent: 2008/0074921 (2008-03-01), Kinoshita
patent: 2008/0198651 (2008-08-01), Kim
patent: 2009/0073771 (2009-03-01), Li
patent: 1020040044938 (2004-05-01), None

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