Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2011-01-25
2011-01-25
Nguyen, Tuan T. (Department: 2824)
Static information storage and retrieval
Floating gate
Multiple values
C365S185180
Reexamination Certificate
active
07876614
ABSTRACT:
The flash memory device of the present invention is configured to program a plurality of bits per unit cell, wherein a program condition of a selected bit is set according to whether a program for the most previous bit to the selected bit for programming is skipped or not skipped. As a result, an accurate programming and reading operation is possible even in case a program for a middle bit is skipped.
REFERENCES:
patent: 5652719 (1997-07-01), Tanaka et al.
patent: 5696717 (1997-12-01), Koh
patent: 5734609 (1998-03-01), Choi et al.
patent: 5768188 (1998-06-01), Park et al.
patent: 5812454 (1998-09-01), Choi
patent: 5841693 (1998-11-01), Tsukiji
patent: 5848009 (1998-12-01), Lee et al.
patent: 5862074 (1999-01-01), Park
patent: 5936887 (1999-08-01), Choi et al.
patent: 5973958 (1999-10-01), Parker
patent: 6137729 (2000-10-01), Choi
patent: 6181606 (2001-01-01), Choi et al.
patent: 6259628 (2001-07-01), Park
patent: 6549457 (2003-04-01), Srinivasan et al.
patent: 6594178 (2003-07-01), Choi et al.
patent: 6725321 (2004-04-01), Sinclair et al.
patent: 6735116 (2004-05-01), Lee et al.
patent: 6772274 (2004-08-01), Estakhri
patent: 6813184 (2004-11-01), Lee
patent: 6853585 (2005-02-01), Lee et al.
patent: 6865110 (2005-03-01), Park
patent: 6986016 (2006-01-01), Patil
patent: 7057942 (2006-06-01), Suda et al.
patent: 7085909 (2006-08-01), Ananthanarayanan et al.
patent: 7120052 (2006-10-01), Shibata et al.
patent: 7164601 (2007-01-01), Mitani et al.
patent: 7215580 (2007-05-01), Gorobets
patent: 7254075 (2007-08-01), Woo et al.
patent: 7388778 (2008-06-01), Hwang
patent: 7466587 (2008-12-01), Wang et al.
patent: 7606069 (2009-10-01), Wang
patent: 2003/0086316 (2003-05-01), Kurjanowicz et al.
patent: 2004/0080979 (2004-04-01), Park
patent: 2005/0007801 (2005-01-01), Barzilai et al.
patent: 2005/0174841 (2005-08-01), Ho
patent: 2005/0246480 (2005-11-01), Fu
patent: 2006/0140011 (2006-06-01), Fong et al.
patent: 2006/0161723 (2006-07-01), Sena et al.
patent: 2007/0106875 (2007-05-01), Mather
patent: 2007/0195597 (2007-08-01), Park et al.
patent: 2009/0237999 (2009-09-01), Li
patent: 2002-511655 (2002-04-01), None
patent: 2006-139864 (2006-06-01), None
patent: 10-0408944 (2003-11-01), None
patent: 10-2004-0098642 (2004-11-01), None
patent: 10-2005-0004142 (2005-01-01), None
Jung et al., “A 3.3-V Single Power Supply 16-Mb Nonvolatile Virtual DRAM Using a NAND Flash Memory Technology,” IEEE Journal of Solid-State Circuits, vol. 32, No. 11, Nov. 1997, pp. 1748-1757.
Takeuchi et al., “A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories,” IEEE Journal of Solid-State Circuits, vol. 33, No. 8, Aug. 1998, pp. 1228-1238.
Tanaka et al., “A 3.4 Mbyte/sec Programming 3-Level NAND Flash Memory Saving 40% Die Size Per Bit,” 1997 Symposium on VLSI Circuits Digest of Technical Papers, pp. 65-66.
European Search Report, European Application No. 06004699.2, Sep. 1, 2006.
Chae Dong-Hyuk
Kang Dong-Ku
Lee Seung-jae
Myers Bigel & Sibley & Sajovec
Nguyen Tuan T.
Samsung Electronics Co,. Ltd.
LandOfFree
Multi-bit flash memory device and program and read methods... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multi-bit flash memory device and program and read methods..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-bit flash memory device and program and read methods... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2708442