Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2000-11-27
2001-10-16
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Floating gate
Multiple values
C365S185050, C365S185170, C257S315000, C257S316000
Reexamination Certificate
active
06304484
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to a flash memory cell. More particularly, it relates to a multi-bit flash memory cell and programming method using the same capable of storing information of more than 2 states at a single flash memory cell.
BACKGROUND OF THE INVENTION
In a conventional memory cell, 1 bit, i.e., only 2 states could be stored at a single memory cell. Thus, in order to reduce the size of a chip, the size of the chip per unit must be reduced. In order to reduce the size of the chip per unit, however, difficulties in various processes are accompanied its cost is increased. Therefore, if data of more than two bits is stored at a single cell, the size of the cell could be reduced to more than half.
In a flash memory cell, there have attempted to develop thus multi-bit cell. Recently, cells implemented in various methods have been reported. As one of the methods reported conventionally, there exists a method by which a floating gate is divided into more than two and the number of electrons in the floating gate is adjusted depending on the programming condition to implement a multi-bit cell. This method, however, is difficult in process and increases the size of the cell per unit, thus counterbalancing the advantage of implementing a multi-bit cell. Also, there is a difficulty in constructing a circuit because the method requires a high voltage upon programming. Further, there is a possibility that reliability of the device is degraded because the method uses a high voltage inside the circuit.
As another method for implementing a multi-bit cell, there is a method of manufacturing a cell, by defining a program verification condition corresponding to
4
states while controlling a program bias or a pulse. This method, however, makes circuits for implementing various program conditions complicated. Further, if the program verification condition is subdivided to perform a program, there is a disadvantage that the time required for the program verification becomes long.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a multi-bit flash memory cell and programming method using the same, which can store information of various states by interchangeably programming a drain and a source in a cell array of virtual ground type, in a structure in which that two types of cells look like connected serially by doping a floating gate in a flash memory cell with two regions of a N type and a P type.
In order to accomplish the above object, a multi-bit flash memory cell according to the present invention is characterized in that it comprises a floating gate electrically isolated from a semiconductor substrate by a gate oxide film, one side of the floating gate has a first doping region and the other side of the floating gate has a second doping region, a control gate electrically isolated from the floating gate by a dielectric film and overlapped with the floating gate in a self alignment manner, a first junction region formed at the semiconductor substrate outside the first doping region in the floating gate, and a second junction region formed at the semiconductor substrate outside the second doping region in the floating gate.
Also, a method of programming a multi-bit flash memory cell according to the present invention, having a structure in which a floating having N-type and P-type doping regions is formed, a gate electrode consisted of a control gate formed on said floating gate is formed and first and second junction regions are formed on both sides of said gate electrode is characterized in that assuming that an initial state where a programming operation is not performed is a ‘00’ state, the first junction region and the second junction region are programmed with a ‘01’ state and a ‘11’ state, respectively, by switching a source voltage and a drain voltage applied to the first and second junction regions, respectively; and the first junction region and the second junction region are programmed with a ‘11’ state by applying a programming voltage for a longer time than when the programming into the ‘10’ state is performed.
The present invention forms a floating gate wherein two regions; a N-type doping region and a P-type doping region are divided when forming polysilicon used for a floating gate. In case that a gate material of a N-type is used, the threshold voltage can be differently adjusted since its work function is different from that of a substrate. In this case, the programming efficiency of the N-type doping side and the P-type doping side is different. Thus, if they are programmed under same conditions, their thresholds to be attained are different. The present invention can use the difference of the threshold voltages thus implemented differently as the threshold voltage in the intermediate step and uses a general erase state and a general program state as an erase state and a complete program state, respectively. The general program state performs the programming using the junction having good program efficiency as a drain side.
At this time, the verification condition is same to the complete program state. Thus implemented cell performs the programming operation while the source and the drain are switched when viewed from the unit cell. Therefore, it can select the source and the drain depending on the program condition, since the array is constructed in a virtual ground type.
REFERENCES:
patent: 5753945 (1998-05-01), Kojima
patent: 5789777 (1998-08-01), Kojima
patent: 5949711 (1999-09-01), Kazerounian
patent: 5999453 (1999-12-01), Kawata
patent: 6151248 (2000-11-01), Harari et al.
Chang Sang Hoan
Choi Seoung Ouk
Shim Keon Soo
Shin Jin
Dinh Son T.
Hyundai Electronics Industries Co,. Ltd.
Pennie & Edmonds LLP
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