Multi-bit error correction scheme in multi-level memory...

Details Multi-bit error correction scheme in multi-level memory... Multi-bit error correction scheme in multi-level memory...

2011-06-28

2011-06-28

Abraham, Esaw T (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C365S185030, C365S185090

Reexamination Certificate

active

07971123

ABSTRACT:
A method, system, and computer software product for operating a memory cell collection. Memory cells in the collection store binary multi-bit values delimited by characteristic parameter bands of a characteristic parameter. In one embodiment, a comparing unit compares a retrieved count and a stored count for each binary multi-bit value. The retrieved count, equal to the number of occurrences the binary multi-bit value, is retrieved from the memory cell collection. The stored count, equal to the number of occurrences the binary multi-bit value, is stored in the memory cell collection. An error correction unit then assigns the error memory cell(s) a corrected binary multi-bit value with the characteristic parameter value within the characteristic parameter band adjacent to the characteristic parameter band associated with the retrieved binary multi-bit value such that the retrieved count of each binary multi-bit value is equal to the stored count of each binary multi-bit value.

REFERENCES:
patent: 5394362 (1995-02-01), Banks
patent: 5550849 (1996-08-01), Harrington
patent: 5621682 (1997-04-01), Tanzawa et al.
patent: 7561465 (2009-07-01), Hancock et al.
patent: 7809994 (2010-10-01), Gorobets

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