Multi-bank synchronous semiconductor memory device with easy con

Details Multi-bank synchronous semiconductor memory device with easy con Multi-bank synchronous semiconductor memory device with easy con

1998-02-13

1999-12-07

Nelms, David

Static information storage and retrieval

Read/write circuit

Data refresh

36523003, G11C 700

Patent

active

05999472&

ABSTRACT:
When refresh of a memory bank having a plurality of array banks is instructed, a refresh control circuit carries out the refresh by saving a row address latched in a row address latch circuit and a bank activation signal supplied to a bank drive unit respectively in a row address saving circuit and a bank activating information saving circuit. After the refresh completes, each array bank is returned to its original state before the refresh instruction is supplied, according to the saved row address and bank activate information. Accordingly, a synchronous semiconductor memory device in which the penalty at the time of the refresh is reduced is provided.

REFERENCES:
patent: 4933907 (1990-06-01), Kumanoya et al.
patent: 5463590 (1995-10-01), Watanabe

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