Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2001-03-30
2004-04-20
Thai, Xuan M. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
Reexamination Certificate
active
06725314
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to memory subsystems and, more particularly, to memory module placement on a memory bus.
2. Description of the Related Art
Memory modules and their corresponding connector sockets for expanding memory within computer systems and other data processing systems are well known. Generally speaking, in-line memory modules include a printed circuit board on which a plurality of memory chips such as dynamic random access memories (DRAMs) are surface mounted. A connective portion along one edge of the printed circuit board is adapted for insertion into a mating (i.e. accommodating) space of a connector. A plurality of contact pads (also called pins) on the connective portion mates with a plurality of corresponding contacts inside the accommodating space of the connector to provide for the transfer of electrical signals between the memory module and the rest of the computer or data processing system.
Two commonly used memory modules are single in-line memory modules (SIMMs) and dual in-line memory modules (DIMMs). On a SIMM, the connective portion usually includes a plurality of contact pads on either the front side of the edge of the printed circuit board or on both the front and back sides of the printed circuit board. In configurations that include contact pads on both the front and back sides of a SIMM, opposing contact pads on the two sides are typically shorted together and therefore carrying the same electrical signal. On a DIMM, the contacts are positioned in the connective portion on both the front and back sides of the printed circuit board. At least some of the opposing contact pads on the two sides of the printed circuit board of a DIMM are configured to carry differing electrical signals, thereby increasing the signal density without necessitating smaller contact pads or a larger printed circuit board.
In many systems, the memory module connectors are mounted on a motherboard or system board such that the memory modules connect to a memory bus one row after another or in a daisy chain. For systems containing a small number of memory modules, or a narrow data bus, the daisy chain configuration may not present any problems. However, as described in greater detail below in conjunction with
FIG. 1
, in systems with a wide data bus and with many memory modules, a daisy chain configuration may present problems.
Turning to
FIG. 1
, a diagram of one embodiment of a memory subsystem configuration using a wide data bus is shown. A processor
10
is coupled to a memory controller
20
through a system bus
15
. Memory controller
20
is coupled to memory modules
25
-
28
A and
25
-
28
B through a memory bus
25
.
In the illustrated embodiment, memory bus
25
includes a data bus which contains 576 data lines. The 576 data lines are subdivided into data paths of 144 lines each. Memory modules
25
-
28
A and
25
-
28
B are arranged to form two memory banks: A and B, respectively. Each memory bank is associated with a particular range of addresses in memory. Each memory module is associated with a particular data path. For example, in memory bank A: Memory module
25
A is coupled to data path
1
, lines
0
-
143
. Memory module
26
A is coupled to data path
2
, lines
144
-
287
. Memory module
27
A is coupled to data path
3
, lines
288
-
431
. Memory module
28
A is coupled to data path
4
, lines
432
-
575
. Thus, when memory bank A is enabled
25
-
28
A may be accessed to store a data word containing all 576 data bits.
Likewise, in memory bank B: Memory module
25
B is coupled to data path
1
, lines
0
-
143
. Memory module
26
B is coupled to data path
2
, lines
144
-
287
. Memory module
27
B is coupled to data path
3
, lines
288
-
431
. Memory module
28
B is coupled to data path
4
, lines
432
-
575
. Thus when memory bank B is enabled, memory modules
25
-
28
B may be accessed to store a data word containing all 576 data bits. Typically, only one memory bank is enabled at a time.
As shown in
FIG. 1
, memory modules
25
-
28
A are closer to memory controller
20
than memory modules
25
-
28
B. If an additional memory bank were added, it would be further still from memory controller
20
. One problem with this topology is signal degradation on the data paths. In this topology, a given data path is routed to a corresponding memory module of each memory bank. Thus, the respective signals may be reflected and distorted as the distance between memory modules coupled to the same data path is increased. In addition, signal timing to each memory bank may be difficult to control since the length of a data path from the memory controller to one memory bank may be significantly different than the length of the same data path to a different memory bank. While two memory banks are shown in
FIG. 1
, it is noted that other embodiments may have more memory banks. In such embodiments, additional signal degradation may be experienced.
SUMMARY OF THE INVENTION
Various embodiments of a multiple bank memory subsystem employing multiple memory modules are disclosed. In one embodiment, a data processing system may include a processor coupled to a memory subsystem. The memory subsystem includes a memory controller coupled to a memory bus. The memory bus includes a plurality of data paths each corresponding to a separate grouping of data lines. The memory bus is coupled to a first plurality of memory modules that provide storage corresponding to a first memory bank. The first memory bank is configured to store data corresponding to a first range of addresses. The memory bus is also coupled to a second plurality of memory modules that provide storage corresponding to a second memory bank. The second memory bank is configured to store data corresponding to a second range of addresses. A separate memory module of each of the first and the second memory banks is coupled to each data path of the memory bus. Memory modules that are coupled to the same data path are located adjacent to one another without any intervening memory modules coupled to other data paths.
REFERENCES:
patent: 4025903 (1977-05-01), Kaufman et al.
patent: 5228132 (1993-07-01), Neal et al.
patent: 5265218 (1993-11-01), Testa et al.
patent: 5270964 (1993-12-01), Bechtolsheim et al.
patent: 5530623 (1996-06-01), Sanwo et al.
patent: 5796672 (1998-08-01), Pitz et al.
patent: 6202110 (2001-03-01), Coteus et al.
patent: 6209056 (2001-03-01), Suh
patent: 2002/0109528 (2002-08-01), Toda
patent: 2226665 (1988-12-01), None
International search report application No. PCT/US02/10563 mailed Sep. 26, 2002.
Kivlin B. Noäl
Thai Xuan M.
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