Multi-bank memory devices having improved data transfer capabili

Details Multi-bank memory devices having improved data transfer capabili Multi-bank memory devices having improved data transfer capabili

1998-10-13

2000-05-23

Hoang, Huan

Static information storage and retrieval

Addressing

Plural blocks or banks

36523006, 365207, 365 63, 365 51, G11C 800

Patent

active

060672706

ABSTRACT:
Multi-bank memory devices include at least first and second banks of memory, a first bit line sense amplifier (S/A) electrically coupled to the first bank of memory by a first pair of differential bit lines (BL and /BL), a first pair of differential input/output lines (IO and IOB) and a preferred first switch cell which is responsive to both a first bank select signal (.phi.YE1) and a first column select signal (CSL1). The first switch cell electrically connects the first pair of differential bit lines to the first pair of differential input/output lines in a preferred sequence to reduce reading errors. The preferred memory devices also include a second bit line sense amplifier electrically coupled to the second bank of memory by a second pair of differential bit lines, a second pair of differential input/output lines and a second switch cell which is responsive to a second bank select signal (.phi.YE2) and the first column select signal (CSL1). The second switch cell also electrically connects the second pair of differential bit lines to the second pair of differential input/output lines in a preferred sequence to reduce reading errors.

REFERENCES:
patent: 5594704 (1997-01-01), Konishi et al.
patent: 5822268 (1998-10-01), Kirihata
patent: 5870347 (1999-02-01), Keeth et al.
Steven A. Przybylski, "New DRAM Technologies," pp. 219-222, 1996.

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