Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
1999-12-17
2001-01-23
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S230040, C365S051000, C365S063000
Reexamination Certificate
active
06178135
ABSTRACT:
RELATED APPLICATION
This application is related to Korean Application No. 98-59498, filed Dec. 28, 1998, the disclosure of which is hereby incorporated herein by reference.
FIELD OF THE INVENTION
The present invention relates to integrated circuit devices and methods of operating integrated circuit devices, and more particularly to integrated circuit memory devices and methods of operating integrated circuit memory devices.
BACKGROUND OF THE INVENTION
Dynamic random access memory (DRAM) devices typically utilize sense amplifiers to facilitate efficient reading and writing operations. Such sense amplifiers may be referred to as input/output sense amplifiers and may be constructed in a manner similar to the sense amplifiers described in commonly assigned U.S. Pat. Nos. 5,701,268 to Lee et al. and 5,953,259 to Yoon et al., the disclosures of which are hereby incorporated herein by reference.
In multi-bank memory devices, dedicated data buses are typically provided so that data being read from a respective memory bank or written to a respective memory bank can be sensed and amplified by a dedicated group of sense amplifiers. Thus, for example, a multi-bank memory device having four banks of memory may include four dedicated data buses and four dedicated groups of sense amplifiers where each group of sense amplifiers operates on data being passed to or received from a respective memory bank. Unfortunately, the use of dedicated data buses and dedicated sense amplifiers reduces layout efficiency, particularly as the storage capacity of the memory banks increase. Accordingly, notwithstanding conventional multi-bank memory devices, there continues to be a need for improved data bus and sense amplifier circuits that can used with large memory banks and have reduced layout area requirements.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved integrated circuit memory devices and methods of operating same.
It is another object of the present invention to provide integrated circuit memory devices that can efficiently handle multi-bank reading and writing operations and methods of operating same.
It is still another object of the present invention to provide integrated circuit memory devices having reduced layout area requirements and methods of operating same.
These and other objects, advantages and features of the present invention are provided by integrated circuit memory devices that include a plurality of memory banks and a plurality of data buses that are connected to the memory banks in a preferred manner to enable the efficient use of a reduced number of shared sense amplifiers and driver circuits during reading and writing operations. According to a preferred embodiment of the present invention, an integrated circuit memory device is provided having plurality of memory banks therein with each memory bank comprising a plurality of memory blocks. A plurality of data buses are also provided and each of these data buses is preferably coupled to at least two of the memory banks so that shared data reading and data writing operations can be performed in an efficient manner using bank selection switches.
In particular, preferred integrated circuit memory devices comprise first and second memory banks which each have respective pluralities of memory blocks therein. First and second data buses are also provided along with circuitry that provides read data from first and second memory blocks within the first memory bank to the first and second data buses, respectively, during a first read operation and provides read data from second and first memory blocks within the second memory bank to the first and second data buses, respectively, during a second read operation. Accordingly, the first and second data buses are used to transfer read data from the first memory bank and transfer read data from the second memory bank as well. In the event the first data bus comprises a first plurality of pairs of differential data lines, circuitry may also be provided that electrically couples the first plurality of pairs of differential data lines to the first memory blocks within the first memory bank during the first read operation, and electrically couples the first plurality of pairs of differential data lines to the second memory blocks within the second memory bank during the second read operation. This circuitry may also electrically couple a second plurality of pairs of differential data lines within the second data bus to the second memory blocks within the first memory bank during the first read operation, and electrically couple the second plurality of pairs of differential data lines to the first memory blocks within the second memory bank during the second read operation. Based on this aspect of the present invention, it may not be necessary a provide a relatively large data bus dedicated to solely the first memory bank and another relatively large data bus dedicated to solely the second memory bank. Instead, a relatively small data bus having half the width of the dedicated data bus can be coupled to first and second portions of the first and second memory banks, respectively, and another relatively small data bus can be coupled to second and first portions of the first and second memory banks, respectively.
According to another preferred aspect of the present invention, first and second bank selection switches are provided and these first and second bank selection switches are electrically coupled to the first and second data buses, respectively. In addition, a first plurality of sense amplifiers are provided that are electrically coupled to the first bank selection switch and a second plurality of sense amplifiers are provided that are electrically coupled to the second bank selection switch. Based on this aspect of the present invention, the selection switches can be controlled in a preferred manner so that the first and second pluralities of sense amplifiers are both used when data is being read from and written to the first memory bank, and are both used when data is being read from and written to the second memory bank. It is therefore unnecessary to provide a plurality of dedicated sense amplifiers for reading data from and writing data to only a first bank of memory and provide another dedicated plurality of sense amplifiers for reading data from and writing data to only a second bank of memory. Thus, according to the present invention, data buses having reduced size can be used in combination with bank selection switches and a reduced number of sense amplifiers to provide an integrated circuit memory device having reduced layout area requirements.
Another embodiment of the present invention includes preferred methods of operating multi-bank memory devices. These preferred methods include the steps of transferring first read data from first and second memory blocks within a first memory bank (BANK 1) to first and second data buses, respectively, and then transferring the first read data from the first and second data buses to first and second sense amplifiers, respectively. These data buses and sense amplifiers can also be used when transferring second read data from first and second memory blocks within a second memory bank (BANK 2) to the first and second data buses, respectively, and then transferring the second read data from the first and second data buses to the first and second sense amplifiers, respectively. The step of transferring the first read data from the first and second data buses to the first and second sense amplifiers may also comprise the steps of simultaneously transferring a first portion of the first read data from the first data bus through a first selection switch to the first sense amplifier and a second portion of the first read data from the second data bus through a second selection switch to the second sense amplifier. Moreover, these methods may also include the steps of transferring a first portion of first write data from the first sense amplifier to the first data bus while simultaneously transferring a sec
Hoang Huan
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
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