Multi-bank memory device with compensation for line loading

Details Multi-bank memory device with compensation for line loading Multi-bank memory device with compensation for line loading

1997-07-17

1999-07-27

Nelms, David

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36523003, 326108, 326106, G11C 800

Patent

active

059301961

ABSTRACT:
A local column selection line driving circuit in a multi-bank memory device is shown which includes a first transistor coupled between a bank selection line and a circuit node and wherein a gate of the first transistor is coupled to a power supply voltage such that a non-inverting bank selection signal received on the bank selection line precharges the circuit node to a first voltage level. The local column selection line driving circuit also includes a second transistor coupled between a global column selection line and a local column selection line and having a gate terminal coupled to the circuit node such that a global column selection signal received on the global column selection line boosts the circuit node to a voltage level higher than the first voltage level. The circuit node then drives the global column selection signal onto the local column selection line through the second transistor. When multiple memory banks of a memory circuit constructed with the local column selection driving circuit are addressed then the charge consumption of the non-inverting bank selection signal on the bank selection line is compensated and line loading is reduced.

REFERENCES:
patent: 5467032 (1995-11-01), Lee
patent: 5517456 (1996-05-01), Chishiki

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