Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
1999-11-24
2001-12-04
Ho, Hoai V. (Department: 2818)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S051000, C365S205000
Reexamination Certificate
active
06327214
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having sense amplifiers shared by adjacent memory banks.
2. Description of the Related Art
To take full advantage of an improvement in the operational speed of a central processing unit (CPU), the performance of a memory device storing information such as data and programs for the CPU should be correspondingly improved. However, the operational speeds of CPUs have improved so remarkably that the CPUs usually outperform conventional DRAMs, and the operational speed of the DRAM is often slower than the operational speed of the CPU. Multi-bank synchronous DRAMs, which include multiple banks and operate in synchronization with a system clock signal, have been developed to provide higher performance and overcome this problem.
Additionally, recent developments in multimedia applications have increasingly demanded semiconductor memory devices having large bandwidths, i.e., the capability to transmit a large amount of IO data per unit time. Accordingly, semiconductor memory devices having high bandwidths with 16, 32, 64, or more parallel bits have been developed. However, memory devices having a high bandwidth require many data lines for transmitting data. In particular, a double data rate synchronous DRAM, which outputs twice the amount of data per clock cycle, normally requires twice as many data lines. The increase in the number of data lines directly increases the area of a DRAM chip. Since the enlargement of the chip area increases the manufacturing cost, efficient data line use and layout are sought to reduce the chip area of a semiconductor memory device.
SUMMARY OF THE INVENTION
In accordance with an aspect of the present invention, an integrated circuit memory device such as a DRAM has fewer data lines. This reduces the chip area of the memory device.
According to one embodiment of the invention, a memory device such as a DRAM includes a plurality of memory banks, a plurality of global IO lines, and a plurality of IO sense amplifiers. The global IO lines are in the memory banks and transmit data read from the memory banks. The global IO lines from at least two of the memory banks connect to the same sense amplifier so that at least two memory banks share each IO sense amplifier, for selectively sensing and amplifying data received from the global IO lines.
Preferably, each of the IO sense amplifiers includes a plurality of IO sense amplifying units and a plurality of switches. The switches connect selected global IO lines in a memory bank to the corresponding IO sense amplifying units in response to activation of bank selection signals. Each of the plurality of switches typically includes transfer gates that bank selection signals turn on or off.
Each of the plurality of IO sense amplifiers can be shared by two adjacent memory banks or four adjacent memory banks. When four adjacent memory banks share one sense amplifier, two of the four memory banks are preferably on the left and right sides of one column decoder to share the column decoder. The bank selection signals determine which one of the memory banks uses the column decoder during a particular data access.
According to an aspect of the present invention, at least two adjacent memory banks share a sense amplifier, so that the number of sense amplifiers and the number of data lines are reduced. Consequently, the area of a chip is reduced.
REFERENCES:
patent: 5594704 (1997-01-01), Konishi et al.
patent: 5991216 (1999-11-01), Raad et al.
patent: 5991223 (1999-11-01), Kozaru et al.
Lee Chang-Ho
Yoon Hong-Il
Ho Hoai V.
Samsung Electronics Co,. Ltd.
Skjerven Morrill & MacPherson LLP
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