Multi-bank memory accesses using posted writes

Details Multi-bank memory accesses using posted writes Multi-bank memory accesses using posted writes

2011-03-29

2011-03-29

Kim, Hong (Department: 2185)

Static information storage and retrieval

Read/write circuit

Simultaneous operations

C365S189080, C365S189120, C365S233100, C711S167000, C711S168000, C711S169000

Reexamination Certificate

active

07916554

ABSTRACT:
Systems and methods for reducing delays between successive write and read accesses in multi-bank memory devices are provided. Computer circuits modify the relative timing between addresses and data of write accesses, reducing delays between successive write and read accesses. Memory devices that interface with these computer circuits use posted write accesses to effectively return the modified relative timing to its original timing before processing the write access.

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