Coded data generation or conversion – Converter calibration or testing
Reexamination Certificate
2001-05-22
2002-10-01
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Converter calibration or testing
C341S155000
Reexamination Certificate
active
06459394
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the offset calibration and auto-zeroing, and more particularly to offset calibration and auto-zeroing in flash analog to digital converters utilized in data transmission systems such as, for example, data communications channels and optical disc data storage systems using data channel circuits.
2. Description of Related Art
In many data detection circuits an electrical signal-is received from a data storage media, such as a CD-ROM, DVD, or other optical disk, magnetic hard disk, magnetic tape etc. In the case of optical disks, the electrical signal is generated from light that is reflected off an optical disk and converted to electrical pulses. The electrical pulses may then be transmitted to a data detection circuit for further signal processing to recover the data in a useable form. Data detection circuits may also be combined with circuitry for write operations. For example, circuitry for both read and write operations may be combined read/write channel circuits utilized with magnetic hard disks. In contrast, some optical disks are utilized in read only systems and thus the data detection circuit need not be combined with write circuitry. In general, both read only and read/write data detection circuits may also include servo circuitry.
Decoding the pulses into a digital sequence can be performed by a simple peak detector in an analog read channel or, as in more recent designs, by using a discrete time sequence detector in a sampled amplitude read channel. Discrete time sequence detectors are preferred over simple analog pulse detectors because they compensate for intersymbol interferences (ISI) and, therefore, can recover pulses recorded at high densities. As a result, discrete time sequence detectors increase the capacity and reliability of the storage system.
There are several well known discrete time sequence detection methods for use in a sampled amplitude read/write channel circuit including discrete time pulse detection (DPD), partial response (PR) with Viterbi detection, partial response maximum likelihood (PRML) sequence detection, decision-feedback equalization (DFE), enhanced decision-feedback equalization (EDFE), and fixed-delay tree-search with decision-feedback (FDTS/DF). When discrete methods are utilized for sampled amplitude read channel systems, an analog to digital converter (ADC) is typically utilized to convert the high frequency data which is contained on disk.
One type of ADC which may be utilized to convert high frequency disk data is a flash ADC. Such an ADC may contain multiple comparators for conversion of the analog data to digital data. A flash ADC may be designed in a number of manners. For example, an exemplary six bit flash analog to digital converter
100
is shown in FIG.
1
. The ADC
100
includes an analog input
102
and a reference voltage input
104
. The reference voltage is divided into 2
n
separate voltages through a series of resistors
106
which form a resistor voltage divider. Output taps are provided from the resistor voltage divider to provide reference voltage inputs
108
to a series of 2
n
−1 comparators
110
. The output of an ADC having 2
n
reference voltages and 2
n
−1 comparators will have n bits. In one common ADC, illustrated in
FIG. 1
in which n equals 6, sixty-four separate voltages are provided through sixty-four resistors
106
(each voltage varying by {fraction (1/64)} of the reference voltage
104
from the adjacent resistor) to inputs to the sixty-three comparators
110
. The analog input
102
which is to be converted to a digital value is provided through another input to each of the comparators
110
. Each comparator
110
receives control signals as shown by a control bus line
112
. The control signal may include a clock signal operating at the system read operation clock speed (for example typically between 50 MHz and 1 GHz) and other control signals. The output of each comparator
110
is a binary state (high or low) which indicates whether the analog input
102
is greater than or less than the particular reference voltage
108
that is input to the comparator
110
. The outputs
112
of the comparators
110
, forming a thermometer code, are provided to digital encoding logic
114
. By observing where the outputs of the comparators
110
change from one digital state to the other, the encoder
114
determines between which two reference voltages the analog input lies and provides a 6-bit digital representation of a voltage that represents, for example, the lower or higher reference voltage or a midpoint voltage. The 6-bit representation may then be provided, through clocked D flip-flops
116
, on an output line as the ADC output
118
. The digital encoding logic
114
may also include bubble suppression logic. It will be appreciated that n can be an integer other than 6. However, 6-bit ADCs are commonly employed in optical storage devices, such as that which may incorporate the ADC
100
of
FIG. 1
, and n=6 will be used to illustrate the ADCs herein.
In order to accurately convert the high frequency analog data, it is desirable that the comparators exhibit very little electrical variation from ideal operation even in the presence of “offsets”. Many sources exist for offsets including mismatch between two devices (for example transistors, resistors, capacitors, etc.) which, though intended to be identical, vary to one degree or another due to limitations of fabrication processes.
One approach to compensate for such offsets is to utilize a DC auto-zero operation.
FIG. 2
shows an example of a typical comparator configuration in a flash ADC
200
. The ADC circuit
200
contains a gm stage
202
capacitively coupled to an analog input and reference levels through input switches. The ADC circuit
200
is shown differentially with two inputs and two reference voltages plus two outputs. During normal operation, the gm stage
202
, the switches SW
1
and SW
2
, and the two input capacitors C
1
and C
2
act as an integrator, integrating the input signal minus the reference for a fixed amount of time. The output of the integrator is transmitted to a latch stage
204
to be converted to a digital signal when a latch clock is applied. The digital signal will be one if the positive output is higher than the negative output and a zero if the negative output is higher than the positive output. Also included is a calibration circuit
208
to remove offsets and achieve higher performance with noise, clock feedthrough, offsets, and other circuit non-idealities. Auto-zero puts an initial voltage across the input capacitors C
1
and C
2
at regular intervals to set the appropriate reference across the input and to remove offsets in the gm stage
202
. Auto-zero should repeated in order to reacquire the reference once the capacitance has leaked enough of its previous charge.
The ADC usually operates in a “normal mode”. Periodically (about every 475 &mgr;s), it enters an auto-zero (“AZ”) mode lasting about 50 ns. It also enters a calibration mode lasting about 1 clock periods following each AZ operation.
FIGS. 3A-3C
show exemplary timing signals for all three modes of operation. In
FIG. 3A
, representing the normal operation, signals SIG and REF, being complements of each other, are high and low, respectively; the input is sent to the comparator. AZ and CAL are both low and the signal INT and LATCH are clocked. In this configuration, the input minus the reference is integrated while INT is high; then LATCH goes high to latch the output to a digital state.
FIG. 3B
illustrates the timing of an AZ sequence. INT and LATCH have the same timing as shown in
FIG. 3A
; however, REF is brought high for several system clock cycles while SIG simultaneously low. These signals cause the input to switch to the reference signal which is tied to the resistor ladder reference. After REF is brought high, AZ is pulled high and held high for about 50 ns, then AZ goes low before the REF signal goes low to store the reference le
Baird Rex
Kostelnik Matthew M.
Nadi Itani R.
Wesley Mokry
Cirrus Logic Inc.
Jean-Pierre Peguy
Shifrin Esq. Dan A.
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