Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – With rotor
Reexamination Certificate
1999-02-26
2002-10-01
Le, N. (Department: 2858)
Electricity: measuring and testing
Measuring, testing, or sensing electricity, per se
With rotor
Reexamination Certificate
active
06459259
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor device testing apparatus suitable for testing semiconductor integrated circuit elements which are typical of semiconductor devices, and more particularly to a semiconductor device testing apparatus of the type in which semiconductor devices are transported to a testing section or test section where they are tested for their electrical characteristics, followed by being carried out of the test section and then being sorted out into conforming articles and non-conforming articles on the basis of the test results, and to a test tray for use in the IC tester in which the tray is moved in a circulating manner along a predetermined path of transport
BACKGROUND ART
Many semiconductor device testing apparatuses (commonly called IC tester) for measuring the electrical characteristics of semiconductor devices to be tested (commonly called DUT (device under test)) by applying a signal of a predetermined test pattern to the devices have a semiconductor transporting and handling (processing) apparatus (commonly called handler) integrally incorporated therein for transporting semiconductor devices to a testing section where they are brought into electrical contact with device sockets on the tester head of the testing apparatus (a component of the testing apparatus for supplying and receiving various electrical signals for testing purposes), followed by carrying the tested semiconductor devices out of the testing section and sorting them out into conforming and non-conforming articles on the basis of the test results. The semiconductor device testing apparatus having integrated therein the handler of the type described above is herein termed simply “IC tester”. In the following disclosure the present invention will be described by taking semiconductor integrated circuit elements (which will be referred to as IC hereinafter) which are typical of semiconductor devices by example for the convenience of explanation.
First, the general construction of one example of the prior art semiconductor device testing apparatus (which will be referred to as IC tester hereinafter) will be described with reference to FIG.
11
.
FIG. 11
is a plan view illustrating the general construction of the IC tester with a plurality of test trays
3
within a soak chamber
41
and an exit chamber
5
shown in a perspective view. In addition to a constant temperature chamber
4
including the soak chamber
41
and a testing section
42
, and the exit chamber
5
(also known as heat-removal/cold-removal chamber), the illustrated IC tester comprises a storage section
11
for storing universal trays (also known as customer trays)
1
loaded with ICs to be tested and universal trays
1
loaded with ICs already tested and sorted, a loader section
7
where ICs being tested are transferred from the universal trays (customer trays)
1
and reloaded onto a test tray
3
, and an unloader section
8
where the tested ICs which have been carried on the test tray
3
out through the exit chamber
5
subsequently to undergoing a test in the testing section
42
of the constant temperature chamber
4
are transferred from the test tray
3
to the universal tray
1
to be reloaded on the latter. The unloader section
8
is generally configured to sort tested ICs based on the data of the test results and load them on the corresponding universal trays.
The soak chamber
41
of the constant temperature chamber
4
is designed for imposing temperature stresses of either a predetermined high or low temperature on ICs under test loaded on a test tray
3
in the loader section
7
while the testing section
42
is designed for executing electrical tests of the ICs under the predetermined temperature stress imposed in the soak chamber
41
. In order to maintain the ICs loaded with temperature stresses of either a predetermined high or low temperature at that temperature during the test, the soak chamber
41
and testing section
42
are both contained in the constant temperature chamber
4
capable of maintaining the interior atmosphere at a predetermined temperature.
The illustrated IC tester is configured such that the soak chamber
41
and testing section
42
of the constant temperature chamber
4
and the exit chamber
5
are arranged in the order named from left to right as viewed in the drawing (referred to as X-axis direction herein) while the loader section
7
and unloader section
8
are located in front of the constant temperature chamber
4
and the exit chamber
5
(downward in the upward-downward direction as viewed in the drawing (referred to as Y-axis direction herein) which is perpendicular to the X-axis direction). As is apparent from
FIG. 11
, the loader section
7
is located in front of the soak chamber
41
of the constant temperature chamber
4
while the unloader section
8
is located in front of the testing section
42
and the exit chamber
5
.
The test tray
3
is moved in a circulating manner from and back to the loader section
7
sequentially through the soak chamber
41
and the testing section
42
in the constant temperature chamber
4
, the exit chamber
5
, and the unloader section
8
. In this path of circulating travel, there are disposed a predetermined number of test trays
3
which are successively moved in the directions as indicated by thick cross-hatched arrows in
FIG. 11
by a test tray transport, not shown.
A test tray
3
, loaded with ICs being tested in the loader section
7
, is conveyed from the loader section to the constant temperature chamber
4
, and then delivered to the soak chamber
41
through an inlet port formed in the front wall of the constant temperature chamber
4
. The soak chamber
41
is equipped with a vertical transport mechanism which is configured to support a plurality of (say,
5
) test trays
3
in the form of a stack with predetermined spacings between successive trays. In the illustrated example, a test tray newly received from the loader section
7
is supported at the top of the stack while the lowermost test tray is delivered to the testing section
42
which on the left-hand side (upstream side) in the X-axis direction, adjoins and communicates with the lower portion of the soak chamber
41
. It is thus to be appreciated that test trays
3
are delivered out in the direction perpendicular to that in which they have been introduced.
ICs being tested are loaded with either a predetermined high or low temperature stress as the associated test tray
3
is moved sequentially from the top to the bottom of the stack by vertically (which is referred to as Z-axis direction) downward movement of the vertical transport mechanism and during a waiting period until the testing section
42
is emptied. In the testing section
42
there is located a tester head, not shown. The test tray
3
which has been carried one by one out of the constant temperature chamber
4
is placed onto the tester head where a predetermined number of ICs out of the ICs under test loaded on the test tray are brought into electrical contact with device sockets (not shown) mounted on the tester head. Upon completion of the test on all of the ICs placed on one test tray through the tester head, the test tray
3
is conveyed to the right side (downstream) in the X-axis direction to the exit chamber
5
where the tested ICs are relieved of heat or cold.
Like the soak chamber
41
as described above, the exit chamber
5
is also equipped with a vertical transport mechanism adapted to support a plurality of (say, five) test trays
3
stacked one on another with predetermined spacings therebetween. In the illustrated example, a test tray newly received from the testing section
42
is supported at the bottom of the stack while the uppermost test tray is discharged to the unloader section
8
. The tested ICs are relieved of heat or cold to be restored to the outside temperature (room temperature) as the associated test tray
3
is moved sequentially from the bottom to the top of the stack by vertically upward movement of the vertical transpor
Ito Akihiko
Kobayashi Yoshihito
Masuo Yoshiyuki
Yamashita Tsuyoshi
Advantest Corporation
Kerveros James
Morrison & Foerster / LLP
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