Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...
Reexamination Certificate
2005-03-29
2005-03-29
Le, Don (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Having details of setting or programming of interconnections...
C365S189120
Reexamination Certificate
active
06873180
ABSTRACT:
FIFO queues enable multiple accesses to data stored therein. A release pointer points to a queue location containing previously read data until a release signal is asserted that changes the release pointer while a read pointer is used to read data from the queue. The repeat signal allows the read pointer to reread previously read data. Asserting the repeat signal sets the read pointer to the value of the release pointer. Once data is no longer needed, the release signal is asserted, causing the release pointer to be incremented with the read pointer thereby freeing memory locations. FIFO queues may comprise multiple release pointers, multiple release and multiple repeat signals. FIFO queues may also comprise a switch signal, which causes the read pointer to switch values with a release pointer. FIFO queues may comprise multiple read pointers and an input signal for determining which read pointer is used.
REFERENCES:
patent: 5710943 (1998-01-01), Burton et al.
patent: 6172927 (2001-01-01), Taylor
patent: 6314478 (2001-11-01), Etcheverry
Le Don
Schwegman Lundberg Woessner & Kluth P.A.
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