MRAM without isolation devices

Details MRAM without isolation devices MRAM without isolation devices

2002-01-18

2003-01-28

Mai, Son (Department: 2818)

Static information storage and retrieval

Systems using particular element

Magnetoresistive

C365S171000, C365S173000

Reexamination Certificate

active

06512689

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to magnetoresistive memories and more particularly, to MRAM array architecture designed so that isolation devices are not required.
BACKGROUND OF THE INVENTION
Thin film Magnetoresistive Random Access Memories (MRAMs) can be fabricated in a variety of memory cell embodiments, including a Magnetic Tunneling Junction (MTJ) cell. Since the MTJ cell is the easiest to manufacture and use, it will be used as the primary example throughout this disclosure, with the understanding that the various concepts also apply to other MRAM cells and arrays. The MTJ cell essentially consists of a pair of magnetic layers with an insulating layer sandwiched therebetween. One of the magnetic layers has a fixed magnetic vector and the other magnetic layer has a changeable magnetic vector that is either aligned with or opposed to the fixed magnetic vector. When the magnetic vectors are aligned the resistance of the MTJ cell, i.e. the resistance to current flow between the magnetic layers, is a minimum and when the magnetic vectors are opposed or misaligned the resistance of the MTJ cell is a maximum.
Data is stored in the MTJ cell by applying a magnetic field to the MTJ cell directed so as to move the changeable magnetic vector to a selected orientation. Generally, the aligned orientation can be designated a logic 1 or 0 and the misaligned orientation is the opposite, i.e., a logic 0 or 1. Stored data is read or sensed by passing a current through the MTJ cell from one magnetic layer to the other. The amount of current passing through the MTJ cell, or the voltage drop across the MTJ cell, will vary according to the orientation of the changeable magnetic vector. Additional information as to the fabrication and operation of MTJ memory cells can be found in U.S. Pat. No. 5,702,831, entitled “Multi-Layer Magnetic Tunneling Junction Memory Cells”, issued Mar. 11, 1998, and incorporated herein by reference.
In most prior art circuits, an isolation device, generally a transistor in series or in parallel with each magnetoresistive device in a memory array, is included to avoid leakage paths throughout the memory array. In most instances the magnetoresistive device and the isolation device are fabricated as a single unit. For example, an isolation transistor is usually fabricated on a semiconductor substrate and the associated magnetoresistive device is fabricated on the isolation transistor so as to be connected internally. One of the problems in this structure is the amount of manufacturing effort required to produce the combined isolation transistor and magnetoresistive device and the control lines required for operation. Also, the large number of isolation devices and control lines for the isolation devices substantially increases the size of the memory array.
In one prior art memory array, magnetoresistive devices without isolation devices are connected so that one input of a differential amplifier is connected to a target column containing the Magnetoresistive device being read, with the other input connected to ground. Feedback within the differential amplifier clamps the target column to a ground potential. All other columns in the array are grounded (i.e. the bitlines are clamped to ground) by means of column select transistors. The read process is performed by applying a read voltage to the row containing the Magnetoresistive device to be read and to all other magnetoresistive devices in the row. Supposedly, since all columns in the array are at ground potential, no current flows between the magnetoresistive device not being read on deselected rows. A major problem with this architecture is that it fails to equalize target (column being read) and other columns adequately, due to non-idealization of clamp circuits, resulting in sneak paths which yield signal loss and speed degradation.
In another prior art memory array, a target column and an associated reference column are connected through a sense amplifier to an output terminal. The sense amplifier sources bitline current through the target column and the references column and clamps the two columns to the same potential. Changes in the current in the target cell (in the target column) are compared with current through the reference cells (in the reference column). However, it is not clear how the two currents differ when both target and reference magnetoresistance cells are in the same state. Also, due to differences in the paths, target and reference columns will not clamp to exactly the same voltage, resulting in sneak paths.
Accordingly it is highly desirable to provide magnetoresistive memory arrays that do not include isolation devices and which overcome the above described problems.


REFERENCES:
patent: 6341084 (2002-01-01), Numata et al.
patent: 6359805 (2002-03-01), Hidaka
patent: 6418046 (2002-07-01), Naji

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