Static information storage and retrieval – Systems using particular element – Magnetoresistive
Reexamination Certificate
2001-08-27
2002-09-03
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Systems using particular element
Magnetoresistive
C365S157000
Reexamination Certificate
active
06445612
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to magnetoresistive memories and more particularly, to apparatus and a method for reading data stored in magnetoresistive memories.
BACKGROUND OF THE INVENTION
Thin film Magnetoresistive Random Access Memories (MRAMs) can be fabricated in a variety of memory cell embodiments, including a Magnetic Tunneling Junction (MTJ) cell. Since the MTJ cell is the easiest to manufacture and use, it will be used as the primary example throughout this disclosure, with the understanding that the various concepts also apply to other MRAM cells and arrays. The MTJ cell essentially consists of a pair of magnetic layers with an insulating layer sandwiched therebetween. One of the magnetic layers has a fixed magnetic vector and the other magnetic layer has a changeable magnetic vector that is either aligned with or opposed to the fixed magnetic vector. When the magnetic vectors are aligned the resistance of the MTJ cell, i.e. the resistance to current flow between the magnetic layers, is a minimum and when the magnetic vectors are opposed or misaligned the resistance of the MTJ cell is a maximum.
Data is stored in the MTJ cell by applying a magnetic field to the MTJ cell directed so as to move the changeable magnetic vector to a selected orientation. Generally, the aligned orientation can be designated a logic 1 or 0 and the misaligned orientation is the opposite, i.e., a logic 0 or 1. Stored data is read or sensed by passing a current through the MTJ cell from one magnetic layer to the other. The amount bf current passing through the MTJ cell, or the voltage drop across the MTJ cell, will vary according to the orientation of the changeable magnetic vector. Additional information as to the fabrication and operation of MTJ memory cells can be found in U.S. Pat. No. 5,702,831, entitled “Multi-Layer Magnetic Tunneling Junction Memory Cells”, issued Mar. 31, 1998, and incorporated herein by reference.
In some prior art circuits, reading data stored in MTJ cells is achieved by passing a current through a series circuit including a load resistor and the MTJ cell. The current passing through the MTJ cell is controlled by a transistor with a bias voltage on the gate, and an output voltage is obtained at a junction between the load resistor and the current controlling transistor. Also, a bitline and a data line for the MTJ cell (and other MTJ cells in the array) are clamped at a desired voltage by the transistor. There are several major problems with this type of data readout including the fact that the load resistor must be much larger than the resistance of the MTJ cell, which makes operation at low supply voltages very difficult. Also, the operation of the circuit is dependent upon the clamping voltage provided by the transistor and the bias voltage. However, the clamping voltage is a function of the resistance of the MTJ cell, the bias voltage, and the load resistance, any or all of which can vary with a specific readout process, variations in the supply voltage, changes in temperature, changes in the resistance of the MTJ cell, etc. Also, the large load resistance and the other components in this prior art circuit require large chip areas preventing the fabrication of high density memory arrays. Also, the input impedance is high due to the presence of the load resistor.
Some of these problems were overcome in U.S. Pat. No. 6,205,073, entitled “Current Conveyor and Method for Readout of MTJ Memories”. In the '073 patent reference, columns were interspersed or distributed throughout an MTJ array. Each reference column carries a “midpoint” current produced by clamping the reference column to a reference bias voltage such that current flowing through the reference column is at a point between minimum and maximum currents flowing through a target column. The task of generating the reference bias voltage is accomplished by two MTJs and some linear CMOS circuitry. Even though this approach is reliable, it could suffer from CMOS circuitry variations and an inability of MTJs in reference bias generators to closely track MTJs in target and reference columns, since the reference bias generator could be located elsewhere on a chip.
Accordingly it is highly desirable to provide apparatus and a method of generating midpoints (e.g. resistance, current, and/or voltage) for reading or sensing MTJ memory cells which overcomes these problems.
REFERENCES:
patent: 6055178 (2000-04-01), Naji
patent: 6191972 (2001-02-01), Miura et al.
Gilmore Douglas W.
Hoang Huan
Koch William E.
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