MRAM parallel conductor orientation for improved write...

Static information storage and retrieval – Systems using particular element – Magnetoresistive

Reexamination Certificate

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C365S171000, C365S173000, C365S066000, C365S051000

Reexamination Certificate

active

06809958

ABSTRACT:

THE FIELD OF THE INVENTION
The present invention generally relates to an optimal write conductor layout in a magnetic random access memory (MRAM). More particularly, the present invention relates to a write conductor layout wherein the write conductors are in generally parallel alignment as they cross the MRAM memory cell to provide improved half-select margins and to reduce write current requirements.
BACKGROUND OF THE INVENTION
An MRAM device includes an array of memory cells. The typical magnetic memory cell includes a layer of magnetic film in which the magnetization is alterable and a layer of magnetic film in which the magnetization is fixed or “pinned” in a particular direction. The magnetic film having alterable magnetization may be referred to as a data storage layer and the magnetic film which is pinned may be referred to as a reference layer.
Conductive traces (commonly referred to as word lines and bit lines) are routed across the array of memory cells. Word lines extend along rows of the memory cells, and bit lines extend along columns of the memory cells. Located at each intersection of a word line and a bit line, each memory cell stores the bit of information as an orientation of a magnetization. Typically, the orientation of magnetization in the data storage layer aligns along an axis of the data storage layer that is commonly referred to as its easy axis. External magnetic fields are applied to flip the orientation of magnetization in the data storage layer along its easy axis to either a parallel or anti-parallel orientation with respect to the orientation of magnetization in the reference layer, depending on the desired logic state.
The orientation of magnetization of each memory cell will assume one of two stable orientations at any given time. These two stable orientations, parallel and anti-parallel, represent logical values of “1” and “0”. The orientation of magnetization of a selected memory cell may be changed by supplying current to a word line and a bit line crossing the selected memory cell. The currents create magnetic fields that, when combined, can switch the orientation of magnetization of the selected memory cell from parallel to anti-parallel or vice versa.
A selected magnetic memory cell is usually written by applying electrical currents to the particular word and bit lines that intersect at the selected magnetic memory cell. Typically, an electrical current applied to the particular bit line generates a magnetic field substantially aligned along the easy axis of the selected magnetic memory cell. The magnetic field aligned to the easy axis may be referred to as a longitudinal write field. An electrical current applied to the particular word line usually generates a magnetic field substantially perpendicular to the easy axis of the selected magnetic memory cell.
Preferably, only the selected magnetic memory cell receives both the longitudinal and the perpendicular write fields. Other magnetic memory cells coupled to the particular word line usually receive only the perpendicular write field. Other magnetic memory cells coupled to the particular bit line usually receive only the longitudinal write field.
The magnitudes of the longitudinal and the perpendicular write fields are usually chosen to be high enough so that the selected magnetic memory cell switches its logic state when subjected to both longitudinal and perpendicular fields, but low enough so that the other magnetic memory cells which are subject only to either the longitudinal or the perpendicular write field do not switch. An undesirable switching of a magnetic memory cell that receives only the longitudinal or the perpendicular write field is commonly referred to as half-select switching.
Manufacturing variation among the magnetic memory cells often increases the likelihood of half-select switching. For example, manufacturing variation in the longitudinal or perpendicular dimensions or shapes of the magnetic memory cells may increase the likelihood of half-select switching. In addition, variation in the thicknesses or the crystalline anisotropy of data storage layers may increase the likelihood of half-select switching. Unfortunately, such manufacturing variation decreases the yield in manufacturing processes for magnetic memories and reduces the reliability of prior magnetic memories.
Because the word lines and the bit lines operate in combination to switch the orientation of magnetization of the selected memory cell (i.e., to write the memory cell), the word lines and bit lines can be collectively referred to as write lines. Additionally, the write lines can also be used to read the logic values stored in the memory cell.
FIG. 1
illustrates a top plan view of a simplified prior art MRAM array
100
. The array
100
includes memory cells
120
, word lines
130
, and bit lines
132
. The memory cells
120
are positioned at each intersection of a word line
130
with a bit line
132
. Most commonly, the word lines
130
and bit lines
132
are arranged in orthogonal relation to one another and the memory cells
120
are positioned in between the write lines (
130
,
132
), is illustrated in
FIG. 1
b
. For example, the bit lines
132
can be positioned above the memory cells
120
and the word lines
130
can be positioned below.
FIGS. 2
a
through
2
c
illustrate the storage of a bit of data in a single memory cell
120
. In
FIG. 2
a
, the memory cell
120
includes an active magnetic data film
122
and a pinned magnetic film
124
which are separated by a dielectric region
126
. The orientation of magnetization in the active magnetic data film
122
is not fixed and can assume two stable orientations is shown by arrow M
1
. On the other hand, the pinned magnetic film
124
has a fixed orientation of magnetization shown by arrow M
2
. The active magnetic data film
122
rotates its orientation of magnetization in response to electrical currents applied to the write lines (
130
,
132
, not shown) during a write operation to the memory cell
120
. The first logic state of the data bit stored in as memory cell
120
is indicated when M
1
and M
2
are parallel to each other as illustrated in
FIG. 2
b
. For instance, when M
1
and M
2
are parallel a logic “1” state is stored in the memory cell
120
. Conversely, a second logic state is indicated when M
1
and M
2
are anti-parallel to each other as illustrated in
FIG. 2
c
. Similarly, when M
1
and M
2
are antiparallel a logic “0” state is stored in the memory cell
120
. In
FIGS. 2
b
and
2
c
the dialectic region
126
has been omitted. Although
FIGS. 2
a
through
2
c
illustrate the active magnetic data film
122
positioned above the pinned magnetic film
124
, the pinned magnetic film
124
can be positioned above the active magnetic data film
122
.
The resistance of the memory cell
120
differs according to the orientations of M
1
and M
2
. When M
1
and M
2
are anti-parallel, i.e., the logic “0” state, the resistance of the memory cell
120
is at its highest. On the other hand, the resistance of the memory cell
120
is at its lowest when the orientations of M
1
and M
2
are parallel, i.e., the logic “1” state. As a consequence, the logic state of the data bit stored in the memory cell
120
can be determined by measuring its resistance. The resistance of the memory cell
120
is reflected by a magnitude of a sense current
123
(referring to
FIG. 2
a
) that flows in response to read voltages applied to the write lines (
130
,
132
).
In
FIG. 3
, the memory cell
120
is positioned between the write lines (
130
,
132
). The active and pinned magnetic films (
122
,
124
) are not shown in FIG.
3
. The orientation of magnetization of the active magnetic data film
122
is rotated in response to a current I
x
that generates a magnetic field H
y
and a current I
y
that generates a magnetic field H
x
. The magnetic fields H
x
and H
y
act in combination to rotate the orientation of magnetization of the memory cell
120
.
As can be seen, there is a need for an NRAM array which provides improved half-select ma

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