MRAM having memory cell array in which cross-point memory...

Details MRAM having memory cell array in which cross-point memory... MRAM having memory cell array in which cross-point memory...

2005-05-10

2005-05-10

Tran, M. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Magnetoresistive

C365S230060

Reexamination Certificate

active

06891748

ABSTRACT:
A memory cell array is of a hierarchical bit line scheme in which cross-point memory cells that exhibit a magnetoresistive effect are laid out in a matrix, and a read bit line to be used in a data read mode is constituted by a main bit line and a sub bit line. A column select circuit selects a main bit line and connects it to a sense amplifier. A row select circuit selects a word line for each cell unit, and in read operation, sets, in a floating state, word lines to which unselected memory cells connected to the sub bit line to which a selected memory cell is connected are connected, and sets the remaining word lines connected to sub bit lines which do not include the selected memory cell to a potential substantially equal to the main bit line.

REFERENCES:
patent: 6259644 (2001-07-01), Tran et al.
US 2004/0125648 A1—U.S. Appl. No. 10/431,369.*
Roy Scheuerlein, et al., “A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell”, ISSCC 2000 Digest of Technical Paper, 2000, pp. 128-129.

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