Static information storage and retrieval – Systems using particular element – Magnetoresistive
Reexamination Certificate
2003-07-25
2004-09-14
Auduong, Gene N. (Department: 2818)
Static information storage and retrieval
Systems using particular element
Magnetoresistive
C365S171000, C365S173000
Reexamination Certificate
active
06791871
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to an MRAM configuration (MRAM=magnetoresistive RAM) containing a multiplicity of memory cells which are disposed in a memory matrix and each of which contains at least one magnetic tunnel junction (MTJ) layer sequence and a selection transistor. The MTJ layer sequences are in each case located between word lines and bit lines, which run at a distance from one another. The selection transistors are connected to first select lines at their gates for reading from the memory cells and the MTJ layer sequences are connected to second select lines.
In their simplest embodiment, MRAM configurations—also called MRAMs for short hereinafter—contain memory cells which are disposed in a memory matrix and each of which has only the MTJ layer sequence in each case. Such an MTJ layer contains the tunnel barrier layer lying between the soft-magnetic layer and the hard magnetic layer and contains an oxide barrier. What is advantageous about the configuration is its high-density configuration: in a completely ideal manner, only an area of 4 F
2
is required per information content or bit, where F denotes the minimum feature size of the technology used. However, what may be regarded as a major disadvantage of such a configuration of an MRAM configuration is that considerable parasitic currents flow through adjacent cells during read-out on account of the only slight differences in the resistance value (about 15%; see above), with the result that such an MRAM configuration can only be read from very slowly overall.
In order to avoid this disadvantage of the slow—and ultimately also unreliable on account of the parasitic currents—read-out of the MRAM configuration a new configuration has already been proposed, in which each individual memory cell contains an MTJ layer sequence and a selection transistor. What is disadvantageous about this MRAM configuration, however, is that the advantage of a high-density configuration is lost, since it is only possible to achieve an effective cell area of 8 F
2
.
In order to resolve the above conflict between area requirement (“F
2
”) on the one hand, and fast read access without parasitic effects, on the other hand, thought has already been given, in the case of completely different memory configurations, namely DRAM configurations (DRAM=dynamic RAM), to use so-called “shared contacts”, in which one contact of a selection transistor is used by a plurality of memory cells, preferably by two memory cells, and area (“F
2
”) is thus saved. However, this solution cannot be employed for MRAMs, and so the above problem area has also not been solved hitherto.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an MRAM configuration that overcomes the above-mentioned disadvantages of the prior art devices of this general type, which allows a rapid read access with a minimal area requirement.
With the foregoing and other objects in view there is provided, in accordance with the invention, an MRAM configuration. The MRAM configuration includes word lines, bit lines running at a distance from the word lines, first select lines, second select lines, and a multiplicity of memory cells disposed in a memory matrix form. The memory cells contain MTJ layer sequences and selection transistors having gates and drain-source paths. The MTJ layer sequences in each case are disposed between the word lines and the bit lines. The selection transistors are connected to the select lines at the gates for reading from the memory cells. The MTJ layer sequences are connected to the second select lines. In a respective one of the memory cells a respective MTJ layer sequence and a respective drain-source path of a respective one of the selection transistors in each case lie parallel to one another, so that the second select lines being formed by the drain-source paths of the selection transistors lie in series with one another.
In the case of an MRAM configuration of the type mentioned in the introduction, the object is achieved according to the invention by virtue of the fact that in the memory cells the MTJ layer sequence and the drain-source path of a selection transistor in each case lie parallel to one another, so that the second select lines are formed by the source-drain paths of the selection transistors lying in series with one another.
Thus, in the case of the MRAM configuration according to the invention, the selection transistors and the MTJ layer sequences of the individual memory cells lie parallel to one another. The memory cells or “basic elements” are then joined together to form chains, chains that run parallel to one another forming a memory matrix. The selection of a chain in such a memory matrix can be effected by a separate selection transistor. In other words, each individual chain is assigned a separate selection transistor at one end of the chain.
The MRAM configuration according to the invention is written to in a customary manner by applying a corresponding signal in each case to the desired word and bit lines. During read-out, first a chain of the memory matrix is defined by the separate selection transistors. All the transistors of the chain are then activated apart from the transistor of the memory cell whose cell content is to be read. The transistor of the memory cell to be read thus remains turned off. If a current is then sent through the chain of the transistor to be read, the current flows solely through the MTJ layer sequence of the memory cell to be read and through all the selection transistors of the remaining memory cells of the chain. The cell content of the memory cell to be read can thus be determined.
The MRAM configuration according to the invention is distinguished by a low area requirement. In the chain, given a corresponding configuration, a memory cell containing the MTJ layer sequence and a selection transistor lying parallel thereto has an effective cell area of 4 F
2
. The separate selection transistor of a chain must be counted with this, which in turn requires an area of 4 F
2
. For a chain having N memory cells, this results in an effective cell area for each memory cell of 4 F
2
(N+1)/N.
It should be noted that in the case of N=1, that is to say a chain containing just one memory cell, an effective cell area of 8 F
2
is present, which corresponds exactly to the previously known solution containing a series circuit of a selection transistor with an MTJ layer sequence. Therefore, the invention can be used particularly advantageously when, in an MRAM configuration, the condition N>1 is present, which applies, of course, to all the memory cells disposed in memory matrices.
The present invention, in a completely novel manner, departs from the previously customary principle of a series circuit containing an MTJ layer configuration and a selection transistor and proposes a novel concept in which the MTJ layer sequence and the selection transistor in each memory cell lie parallel to one another and are joined together to form chains.
In accordance with an added feature of the invention, selection transistors are provided and each of the second select lines of a chain of the memory cells in the memory matrix lies in series with a separate one of the selection transistors.
In accordance with an additional feature of the invention, the gates of the selection transistors are connected to the first select lines.
In accordance with another feature of the invention, the memory cells have a minimum dimension being 4 F
2
where F denotes a minimum feature size of a technology used.
In accordance with a further feature of the invention, the first select lines are routed above the gates of the selection transistors.
In accordance with a concomitant feature of the invention, the first select lines and the bit lines run parallel to one another.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodi
Freitag Martin
Roehr Thomas
Auduong Gene N.
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Stemer Werner H.
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