Static information storage and retrieval – Systems using particular element – Magnetoresistive
Reexamination Certificate
2001-08-23
2002-07-16
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Systems using particular element
Magnetoresistive
C365S157000
Reexamination Certificate
active
06421271
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a magnetoresistive random access memory (MRAM) configuration having a multiplicity of tunnel magneto-resistance (TMR) memory cells that, in a memory cell field, are connected at their one end with bit lines and are connected at their other end to word lines.
As is known, an MRAM configuration is based on ferromagnetic storage with the aid of the TMR effect: between a word line and a bit line that cross one another in perpendicular fashion, there is located a memory cell formed from a layer stack, having a soft magnetic layer, a tunnel resistance layer, and a hard magnetic layer. The direction of magnetization of the hard magnetic layer is predetermined, while the direction of magnetization of the soft magnetic layer can be set by sending corresponding currents in particular directions through the word line and the bit line. In this way, the soft magnetic layer can be magnetized parallel or antiparallel to the hard magnetic layer. In the case of parallel magnetization, the resistance value of the layer stack is lower than in the case of antiparallel magnetization, which can be evaluated an the state “0” or “1,” or vice versa.
Up to now, essentially two fundamentally different architectures have been proposed for an MRAM.
In what is known as a cross point construction, the individual TMR memory cells are located directly between printed conductors that cross one another and that form bit lines or word lines. In this construction, no semiconductor elements, in particular transistors, are required for the individual memory cells, so that a plurality of layers of such memory cells can unproblematically be provided in memory cell fields stacked one over the other. In this way, very high integration densities can be achieved for an MRAM, on the order of magnitude of 4 F
2
, where n is the number of the individual layers of memory cell fields stacked one over the other and F signifies the surface of the smallest possible structure of the technology used.
In such a cross point construction, parasitic currents necessarily flow through memory cells that are not selected. For this reason, in large memory cell fields the individual TMR memory cells must be provided with a very high resistance in order to enable the parasitic currents to be kept low. As a result of the high resistance of the individual TMR memory cells, the read process is relatively slow.
In the architecture of the prior art, in which transistor cells are provided, a switching transistor is allocated to each individual TMR element with the above layer stack (on this subject, see the reference by M. Durlam et al., titled “Nonvolatile RAM based on Magnetic Tunnel Junction Elements”). In an MRAM having memory cells consisting of such TMR elements with switching transistors, parasitic currents are practically excluded. In this way, the memory cells can be provided with a low resistance of the TMR element, even in large memory cell fields. The read process is also simpler, so that a faster access is possible than is the case given a cross point construction.
However, a disadvantage of Construction with transistor memory cells is the considerably larger dimensions, which run to at least 8 F
2
and higher; in addition, no stacking can be carried out because a transistor, and therewith a silicon surface, is required for each memory cell in a memory cell field.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an MRAM configuration which overcomes the above-mentioned disadvantages of the prior art devices of this general type, in which the advantages of cross point construction are to the greatest possible extent present together with the advantages of transistor memory cells.
With the foregoing and other objects in view there is provided, in accordance with the invention, a magneto-resistive random access memory (MRAM) configuration. The MRAM configuration contains switching transistors with gates, bit lines, word lines, and a memory cell field having a multiplicity of tunnel magneto-resistance (TMR) memory cells each having a first end connected to the bit lines and a second end. The TMR memory cells are divided into groups each containing at least two of the TMR memory cells connected respectively with a same one of the bit lines. The second end of each of the TMR memory cells of each of the groups are connected with one of the switching transistors whose respective gate is connected to a corresponding one of the word lines.
In an MRAM configuration of the type indicated above, the object is inventively achieved in that the other ends of TMR memory cells connected respectively with the same bit line, in groups containing at least two TMR memory cells, are connected with a switching transistor whose gate is connected to the corresponding word line.
Thus, in a complete departure from the previous configuration using transistor memory cells, in the inventive MRAM configuration it is no longer the case that a switching transistor is allocated to each TMR element. Rather, in the inventive MRAM configuration a plurality of TMR memory cells along a bit line are combined to form a group, and a switching transistor is then assigned to the group.
Through the allocation of only one switching transistor to a plurality of TMR memory cells, for example three TMR memory cells, the space required for the transistors can be considerably reduced, so that the architecture used in the inventive MRAM configuration enables a considerable increase of the packing density in the memory cell field.
The inventive MRAM configuration also enables a space-saving layout of the TMR memory cells and of the transistor allocated thereto, by disposing for example one switching transistor under three TMR memory cells.
Of course, however, it is also possible to provide more than three TMR memory cells for one switching transistor. In addition, it is also possible for example to assign only two TMR memory cells to one switching transistor. Finally, such an apportioning of the memory cells of a memory cell field to switching transistors can also be carried out in that, exceptionally, allocations of only one memory cell to a switching transistor can be present. It is therefore essential to the present invention that, in a memory cell field having a multiplicity of memory cells, switching transistors are allocated to the cells in such a way that, for a multiplicity of memory cells of the memory cell field, one switching transistor is respectively assigned to a plurality of memory cells of a respective bit line.
A rapid reading out of the MRAM cells with transistors is then ensured if an absolute difference that is as great as possible is present in the currents obtained during the reading of the two states. That is, the current difference between a parallel state and an antiparallel state of the two magnetic layers should be as great as possible. In order to achieve this, first the resistance of the TMR memory cell, or of the TMR element, should be selected approximately equal to the overall resistance, composed of the switching transistor and the resistance of the lines, that is located in series to this resistance. The smaller the series resistance of the resistance composed of the TMR memory cell and the above overall resistance, the greater becomes the absolute read signal obtained during reading.
As already explained above, in the inventive MRAM configuration, n TMR memory elements are therefore connected in parallel along a bit line, and are connected at its other end with the switching transistor. This has the disadvantage that the signal current flowing through the n TMR memory elements that are located parallel to one another is respectively reduced or “thinned” by this factor n. However, the disadvantage can be at least partially compensated in that there is easily space for a switching transistor under a layout surface for only three TMR memory elements, so that, given an allocation of three TMR memory cells to one switching transistor, a rela
Gogl Dietmar
Schlösser Till
Greenberg Laurence A.
Hoang Huan
Infineon - Technologies AG
Mayback Gregory L.
Stemer Werner H.
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