Active solid-state devices (e.g. – transistors – solid-state diode – Encapsulated – With specified encapsulant
Reexamination Certificate
2000-01-31
2003-07-29
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Encapsulated
With specified encapsulant
C257S787000, C257S788000, C257S789000, C257S795000, C257S737000, C257S738000, C257S780000
Reexamination Certificate
active
06600234
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having bump electrodes and a method of manufacturing the same.
A mounting technology called the face down bonding system is employed in some cases in mounting a semiconductor device consisting of a single semiconductor chip or a semiconductor device called CSP (Chip Size Package) to a circuit substrate. In such a semiconductor device, bump electrodes for connection to, for example, another circuit substrate are mounted directly to a semiconductor substrate or mounted to a semiconductor substrate with an intermediate substrate (interposer) interposed therebetween.
It is customary to manufacture such a semiconductor device by the manufacturing process shown in
FIGS. 11A and 11B
. Specifically, a plurality of bump electrodes
3
are formed on a semiconductor substrate
2
such as a silicon substrate of a wafer state, as shown in FIG.
11
A. Then, a sealing film
4
made of an epoxy resin is formed by a screen printing method, a potting method, a transfer molding method or the like such that the thickness of the sealing film
4
is somewhat larger than the height of the bump electrode
3
. Therefore, under this state, the upper surface of the bump electrode
3
is covered with the sealing film
4
. Then, the upper regions of the sealing film
4
are polished appropriately so as to permit the upper surfaces of the bump electrodes
3
to be exposed to the outside, as shown in FIG.
11
B. After the polishing step, the silicon wafer is separated into individual semiconductor chips in a dicing step (not shown) so as to obtain a semiconductor device
1
provided with bump electrodes.
Solder bumps are formed on the bump electrodes of the semiconductor device
1
thus prepared and these solder bumps are mounted to connection pads of another circuit substrate by a face down bonding method.
FIG. 12
exemplifies the mounted structure thus prepared. The semiconductor substrate
1
comprises a planar and rectangular silicon substrate
2
, and a plurality of connection pads
5
for connection to outer devices are formed on the lower surface of the silicon substrate
2
. An insulating film
6
is formed on the entire lower surfaces of the silicon substrate
2
and the connection pads
5
except the central portions of the connection pads
5
such that the central portions of the connection pads
5
are exposed to the outside via the open portions formed in the insulating film
6
. A wiring substrate metal layer
8
is formed to extend from the exposed lower surface of the connection pad
5
to the lower surface of the insulating film
6
. In this case, the wiring substrate metal layer
8
consists of a connecting portion
8
a
positioned below the connection pad
5
, a connecting pad portion
8
b
positioned in a predetermined portion of the lower surface of the insulating film
6
, and a draw wiring
8
c
formed between the connecting portion and the connecting pad. The bump electrode
3
consisting of copper, gold, etc. is formed on the lower surface of the connecting pad portion
8
b
. Further, the sealing film
4
consisting of, for example, an epoxy resin is formed on the lower surface of the insulating film
6
and the wiring
8
excluding the bump electrode
3
. The solder bump
9
is formed on the lower surface of the bump electrode
3
. It should be noted that the solder bumps
9
of the semiconductor device
1
are bonded to connection pads
11
formed on the upper surface of a circuit substrate
10
consisting of, for example, a glass epoxy by a face down bonding so as to mount the semiconductor device
1
to the circuit substrate
10
.
It should be noted that silicon constituting the silicon substrate
2
, the sealing resin constituting the sealing film
4
and the glass epoxy constituting the circuit substrate
10
differ from each other in thermal expansion coefficient. Specifically, the thermal expansion coefficient is 2 to 3 ppm/° C. for silicon, 10 to 15 ppm/° C. for the sealing resin and about 15 ppm/° C. for the glass epoxy. What should be noted is that the sealing film
4
and the circuit substrate
10
are close to each other in the thermal expansion coefficient. On the other hand, a difference in the thermal expansion coefficient between the sealing film
4
and the silicon substrate
2
is relatively large. As a result, a relatively large stress derived from the difference in thermal expansion coefficient is generated between the silicon substrate
2
and the sealing film
4
by the change in temperature in the case where the semiconductor device
1
is bonded to the circuit substrate
10
via the solder bumps
9
as shown in FIG.
12
. What should be noted in this connection is that the thickness of the insulating film
4
is equal to the height of the bump electrode
3
. It follows that the bump electrode
3
is incapable of being deformed so as to absorb the stress generated between the silicon substrate
2
and the sealing film
4
, leading to the possibility that a crack may be formed in the bonding portion between the bump electrode
3
and the solder bump
9
or in the bonding portion between the solder bump
9
and connection pad
11
. The formation of such a crack brings about a problem that it is difficult to ensure a satisfactory bonding.
BRIEF SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device comprising bump electrodes formed on a semiconductor substrate and a sealing film, the semiconductor device being mounted to another circuit substrate via the bump electrodes and having a structure for absorbing the stress derived from a difference in thermal expansion coefficient between the semiconductor substrate the circuit substrate and between the semiconductor substrate and the sealing film so as to suppress occurrence of a defective bonding, and a method of manufacturing the particular semiconductor device.
For achieving the object, a first semiconductor device of the present invention is featured in that a sealing film comprising of at least two layers having the thermal expansion coefficients controlled appropriately is formed between adjacent bump electrodes on the semiconductor substrate, and that the thickness of each layer of the sealing film is smaller than the height of the bump electrode. Where the thickness of the entire sealing film is made smaller than the height of the bump electrode, the bump electrode projects from the sealing film, and the projecting portion of the bump electrode absorbs the stress derived from the difference in thermal expansion coefficient between the semiconductor substrate and the circuit substrate. A method of manufacturing the semiconductor device of the particular construction comprises the step of forming a laminate film consisting of a protective film formed on a lower surface of a base film and a sealing film formed on the protective film, the sealing film comprising of a plurality of layers, the step of disposing the laminate film thus formed on the bump electrodes, followed by heating under pressure the laminate film to permit the bump electrodes to extend through the sealing film; and the step of peeling off the base film and the protective film to permit the protective film to perform the function of a buffer member, thereby preventing the bump electrodes from being collapsed or damaged.
For achieving the object, a second semiconductor device of the present invention is featured in that the thermal expansion coefficient of the sealing film formed between adjacent bump electrodes on the semiconductor substrate is controlled to differ in its thickness direction such that the thermal expansion coefficient of the sealing film on the side of the semiconductor substrate is close to that of the semiconductor substrate and the thermal expansion coefficient of the sealing film on the side of the circuit substrate is close to that of the circuit substrate. The particular construction permits absorbing the stress derived from a difference in thermal expansion coefficient between the semiconductor s
Kuwabara Osamu
Mihara Ichiro
Wakabayashi Takeshi
Casio Computer Co. Ltd.
Frishauf Holtz Goodman & Chick P.C.
Parekh Nitin
Thomas Tom
LandOfFree
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