Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-10-13
2002-11-05
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S330000, C257S331000, C257S332000, C257S333000, C257S334000, C438S212000, C438S259000, C438S268000
Reexamination Certificate
active
06476443
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to MOSgated semiconductor devices and more specifically, relates to such devices with a trench geometry and a remote contact structure.
BACKGROUND OF THE INVENTION
MOSgated devices are well known and may have a planar channel geometry or a trench channel geometry.
In the planar geometry version, spaced channel regions are diffused into the surface of a chip and MOSgates cover the invertible channel regions which are coplanar with one another. Such structures are useful over a wide range of breakdown voltages.
In the trench geometry version, invertible channel regions are formed along the vertical walls of U-shaped trenches etched into the silicon surface. A source contact is connected to the channel region and source region for each separate trench unit. Trench devices are preferably used for lower breakdown voltage ratings, for example, less than about 100 volts.
Both planar geometry devices and trench geometry devices may be formed with channel regions of a spaced polygonal or spaced stripe arrangement.
Trench geometry devices have an inherently lower capacitance between gate and drain, and thus a lower charge Q
GD
than planar devices. Since an important figure of merit of a MOSFET is the product of Q
GD
and the on-resistance R
DSON
, trench devices are frequently desired for low voltage applications requiring a minimum switching loss such as the MOSFETs used in low voltage power supplies for supplying power from a battery to a portable electronic device such as a lap top computer.
Trench device geometries have not permitted the best trench density for minimizing the R
DSON
. Therefore, while the trench device has a low Q
GD
, complex manufacturing processes are needed to produce a low R
DSON
as well.
Thus, i t is desirable to provide a trench geometry Mosgated device such as a MOSFET, which has a minimized Q
GD
and R
DSON
but is capable of inexpensive and reliable production techniques.
BRIEF DESCRIPTION OF THE INVENTION
In accordance with the present invention, a novel trench structure and manufacturing process is provided in which both a very low Q
GD
and R
DSON
, is provided through the use of a common polysilicon layer for a plurality of adjacent trenches, with contacts to the source and channel region being remote from the trench areas. As a result, the trenches can be more closely spaced, to increase total channel width per unit area. The Q
GD
is also reduced by the use of a unique trench mesa height and control of the trench bottom relative to the P/N junction which defines the bottom of the invertible channel along the walls of the trench. More specifically, a trench depth (or mesa height) of about 1.8 microns is used, with the trench bottom penetrating the P/N junction by about 0.2 to 0.25 microns.
The novel trench structure is also preferred to have a length less than about 20 microns and a width of about 0.6 microns. The trenches are arranged in parallel, coextensive groups with a spacing greater than about 0.6 microns. The trenches are filled with a common polysilicon layer which acts as the device gate. Each parallel set of trenches are spaced from an adjacent set by a strip of untrenched area running perpendicular to the elongated trenches. The source/base contacts are formed in this strip, remotely from the trench structures, but connected to the channel region and source region for each trench.
By making contact only to the source region, a bidirectional conductive device can be formed.
The novel device lends itself to a simplified manufacturing process having a reduced number of masks and critical mask alignments and has a minimized figure of merit.
REFERENCES:
patent: 5321289 (1994-06-01), Baba et al.
patent: 6037628 (2000-03-01), Huang
A High-Density Ultra-Low Rdson 30 Volt N-Channel Trench FETS for DC/DC Converter Applications, El Segundo CA, pp. 1-4, Sodhi R; Malik R; Asselanis D; and Kinzer D, “Proceedings of International Symposium of Power Semiconductor Devices and ICs (ISPSD)”, May 26, 1999. IEEE Catalog #99CH36312, PP 303-306.
Ultra-Low Rdson 12 v P-Channel Trench MOSFET, El Segundo CA, pp. 1-4, Kinzer D; Asselanis D; and Carta R, “Proceedings of International Symposium of Power Semiconductor Devices and ICs (ISPSD)”, May 26, 1999. IEEE Catalog #99CH36312, PP 307-310.
Integrated Design Environment for DC/DC Converter FET Optimization El Segundo CA, pp. 1-4, Sodhi R; Browh S Sr.; and Kinzer D.; Dallas TX, Martinez R; Stanford CA, Wiemer M, “Proceedings of International Symposium of Power Semiconductor Devices and ICs (ISPSD)”, May 26, 1999. IEEE Catalog #99CH36312, PP 241-244.
International Rectifier Corporation
Kang Donghee
Thomas Tom
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