MOSFETs with differing gate dielectrics and method of formation

Details MOSFETs with differing gate dielectrics and method of formation MOSFETs with differing gate dielectrics and method of formation

2002-01-11

2003-03-04

Wojciechowicz, Edward (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

With means to increase breakdown voltage threshold

With electric field controlling semiconductor layer having a...

C257S497000, C257S506000, C257S511000, C257S521000

Reexamination Certificate

active

06528858

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to semiconductor devices and the fabrication thereof and, more particularly, to a first and a second MOSFET having differing dielectrics a method of formation.
BACKGROUND
A pervasive trend in modern integrated circuit manufacture is to produce semiconductor devices, such as metal oxide semiconductor field effect transistors MOSFETs), that are as small as possible. In a typical MOSFET, a source and a rain are formed in an active region of a semiconductor layer by implanting N-type or P-type impurities in the layer of semiconductor material. Disposed between the source and the drain is a channel (or body) region. Disposed above the body region is a gate electrode. The gate electrode and the body are spaced apart by a gate dielectric layer. It is noted that MOSFETs can be formed in bulk format (for example, the active region being formed in a silicon substrate) or in a semiconductor-on-insulator (SOI) format (for example, in a silicon film that is disposed on an insulating layer that is, in turn, disposed on a silicon substrate).
Although the fabrication of smaller transistors allows more transistors to be placed on a single monolithic substrate for the formation of relatively large circuit systems in a relatively small die area, this downscaling can result in a number of performance degrading effects. For example, certain materials, when used in a down-scaled device, may become electrically leaky and can cause reliability problems. In addition, the fabrication of downscaled devices should be kept within a thermal budget so as to minimize the introduction of device irregularities.
Accordingly, there exists a need in the art for semiconductor devices, such as MOSFETs, that optimize scale and performance. There also exists a need for corresponding fabrication techniques to make those semiconductor devices.
SUMMARY OF THE INVENTION
According to one aspect of the invention, a semiconductor wafer including an NMOS device and a PMOS device. The NMOS device includes a first source, a first drain and a first body formed from a layer of semiconductor material, the first body disposed between the first source and the first drain. The NMOS device also includes a first gate formed over the first body and having a first gate electrode defining a first channel interposed between the first source and the first drain, the first gate electrode separated from the layer of semiconductor material by a high-K gate dielectric. The PMOS device includes a second source, a second drain and a second body formed from the layer of semiconductor material, the second body disposed between the second source and the second drain. The PMOS device also includes a second gate formed over the second body and having a second gate electrode defining a second channel interposed between the second source and the second drain, the second gate electrode separated from the layer of semiconductor material by a standard-K gate dielectric.
According to another aspect of the invention, a method of forming an NMOS device and a PMOS device on a semiconductor wafer. The method includes providing a layer of semiconductor material, forming the NMOS device and forming the PMOS device following NMOS device formation. Forming the NMOS device includes forming a layer of high-K dielectric material over the layer of semiconductor material; forming a first gate electrode for the NMOS device; and forming a first source and a first drain for the NMOS device from the layer of semiconductor material such that the first gate electrode defines a first channel interposed between the first source and the first drain. Forming the PMOS device includes encapsulating the NMOS device with a protective layer; forming a layer of standard-K dielectric material over the layer of semiconductor material; forming a second gate electrode for the PMOS device; and forming a second source and a second drain for the PMOS device from the layer of semiconductor material such that the second gate electrode defines a second channel interposed between the second source and the second drain.


REFERENCES:
patent: 6013553 (2000-01-01), Wallace et al.
patent: 6020024 (2000-02-01), Maiti et al.
patent: 6048769 (2000-04-01), Chau

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