MOSFET with raised STI isolation self-aligned to the gate stack

Details MOSFET with raised STI isolation self-aligned to the gate stack MOSFET with raised STI isolation self-aligned to the gate stack

1994-12-28

1996-07-23

Monin, Jr., Donald L.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257305, 257397, 257623, H01L 2708, H01L 2976, H01L 2900

Patent

active

055392296

ABSTRACT:
A semiconductor structure comprising a transistor having a gate conductor that has first and second edges bounded by raised isolation structures (e.g. STI). A source diffusion is self-aligned to the third edge and a drain diffusion is self-aligned to the fourth edge of the gate electrode.

REFERENCES:
patent: 3936859 (1976-02-01), Dingwall
patent: 4688069 (1987-08-01), Joy et al.
patent: 5173439 (1992-12-01), Dash et al.
patent: 5264716 (1993-11-01), Kenney
T. Furukawa et al., "Process and Device Simulation of Trench Isolation Corner Parasitic Device", Proceedings of the Electrochemical Society Meeting, Oct. 9-14, 1988.
A. Bryant et al., "The Current-Carrying Corner Inherent to Trench Isolation", IEEE Electron Device Letters, vol. 14, No. 8, Aug. 1993.
D. Foty et al., "Behavior of an NMOS Trench-Isolated Corner Parasitic Device at Low Temperature", Proceedings of the Electrochemical Society Meeting, Oct. 1989.
T. Ishijima et al., "A Deep-Submicron Isolation Technology with T-shaped Oxide (TSO) Structure", Proceedings of the IEDM, 1990, p. 257.

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