MOSFET structure with high mechanical stress in the channel

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S365000, C438S197000

Reexamination Certificate

active

07002209

ABSTRACT:
The present invention provides a semiconducting device including at least one gate region including a gate conductor located on a surface of a substrate, the substrate having an exposed surface adjacent the gate region; a silicide contact located adjacent the exposed surface; and a stress inducing liner located on the silicide contact, the exposed surface of the substrate adjacent to the gate region and the at least one gate region, wherein the stress inducing liner provides a stress to a device channel portion of the substrate underlying the gate region. The stress produced on the device channel is a longitudinal stress on the order of about 200 MPa to about 2000 MPa. The present invention also provides a method for forming the above-described semiconducting device.

REFERENCES:
patent: 5447875 (1995-09-01), Moslehi
patent: 6214709 (2001-04-01), Chen
patent: 6709935 (2004-03-01), Yu
patent: 6737308 (2004-05-01), Kim
patent: 6890808 (2005-05-01), Chidambarrao et al.
Jeffrey A. Davis, et al., “Interconnect Limits on Gigascale Integration (GSI) in the 21stCentury”,Proceedings of the IEEE, vol. 89, No. 3, pp. 305-324 (2001).
“Grand Challenges”,The International Technology Roadmap For Semiconductors, pp. 9-15 (2002).
Shinya Ito, et al. “Mechanical Stress Effect of Etch-Stop Nitride and its Impact on Deep Submicron Transistor Design”,IEEE Electron Devices Meeting, 247-250 (2000).

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