Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-07-25
2003-09-16
Smith, Matthew (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C257S330000, C257S341000, C257S345000, C257S401000, C257S774000
Reexamination Certificate
active
06621118
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application is related to Japanese Patent Application No. 2001-240865 filed on Aug. 8, 2001, whose priority is claimed under 35 USC §119, the disclosure of which is incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a MOSFET, a semiconductor device using the MOSFET and a process for producing the semiconductor device. More particularly, the MOSFET can be switched to ON/OFF by applying two kinds of gate voltage and generates an output by AND logic in response to inputs to gates.
2. Description of Related Art
MOS transistors, memory cells and other semiconductor devices have been microfabricated according to the scaling law proposed by J. R. Brews in order to realize high integration.
However, with progress of microfabrication, there arise major tasks in actual devices such as occurrence of leakage current at gate insulating films owing to reduced thickness of the gate insulating films, increase in resistance of source/drain diffusion layers owing to reduced junction depth (Xj) of the source/drain diffusion layers, decrease in punch-through withstand voltage between the source/drain regions owing to a short-channel effect.
Referring to
FIG. 15
, there is proposed a semiconductor device wherein a gate electrode
23
is disposed in a trench formed in a semiconductor substrate
21
of about 0.4 to 0.6 &mgr;m depth with intervention of a gate insulating film
22
so that an effective channel length is increased while a plan-view channel length is decreased. Also by forming a high-concentration region
26
at least below a source region
24
or a drain region
25
, the short-channel effect can be reduced. The high-concentration region
26
is of the same conductivity type as that of the semiconductor substrate
21
and has a higher impurity concentration than that of the semiconductor substrate
21
(see Japanese Unexamined Patent Publication No. HEI 5(1993)-102480).
The high concentration region
26
functions as a punch-through stopper diffusion layer and has a peak of concentration along a dotted line in FIG.
5
. By forming the trench deeper than the high concentration region
26
, the channel region is formed in a low-concentration region. This construction suppresses extension of depletion layers from the source and drain regions
24
and
25
, thereby improving the punch-through withstand voltage.
In this semiconductor device, boron ions are implanted so that the boron concentration has the peak at the depth represented by the dotted line in
FIG. 15
for forming the punch-through stopper diffusion layer. Since boron ions have a large diffusion coefficient, they diffuse in a depth direction into the semiconductor substrate
21
. Accordingly, unless the trench is deep enough, the concentration of the impurity of the same conductivity type as that of the substrate increases in the entire channel region. Consequently, in the channel region, carrier mobility is declined due to scattering by the impurity and a drive current decreases.
Therefore, there is a problem in that the trench needs to be formed deep for increasing the drive current.
Further, in the case where an AND circuit is constructed by use of such a semiconductor device, it is necessary to dispose a diffusion layer between connected two transistors. Therefore, there is a problem in that occupied area increases.
SUMMARY OF THE INVENTION
The present invention provides a MOSFET which comprises a first conductivity type a semiconductor substrate having a trench formed in a surface area thereof, a gate electrode formed on the semiconductor substrate; and a trench gate electrode which is adjacent to the gate electrode and is buried in the trench, and which generates an output by AND logic in response to inputs to the gate electrode and the trench gate electrode, wherein an impurity concentration directly below the gate electrode is higher than an impurity concentration directly below the trench gate electrode.
The present invention also provides a process for manufacturing a semiconductor device comprising the steps of:
(a) implanting impurity ions of a first conductivity type in a semiconductor substrate of the first conductivity type;
(b) forming a gate insulating film, a first conductive film and an insulating film in this order on the semiconductor substrate;
(c) forming a first resist pattern having a desired configuration on the insulating film;
(d) etching the insulating film, the first conductive film and the gate insulating film using the first resist pattern as a mask and further etching the semiconductor substrate to form a trench;
(e) forming a second resist pattern having a desired configuration on the insulating film after removing the first resist pattern;
(f) patterning the insulating film and the first conductive film to form a gate electrode using the second resist pattern as a mask;
(g) forming a trench gate insulating film in the trench;
(h) depositing a second conductive film over the resulting semiconductor substrate including the trench;
(i) etching back the second conductive film so that the second conductive film is buried in the trench, thereby forming a trench gate electrode;
(j) implanting impurity ions of a second conductivity type in the semiconductor substrate using the gate electrode and the trench gate electrode as a mask; and
(k) annealing for activation the resulting semiconductor substrate to form source/drain regions of a second conductivity type and a high-concentration impurity diffusion layer of a first conductivity type directly below the gate electrode
These and other objects of the present application will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
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patent: 4814840 (1989-03-01), Kameda
patent: 5049515 (1991-09-01), Tzeng
patent: 5293084 (1994-03-01), Itoh et al.
patent: 5371023 (1994-12-01), Minami et al.
patent: 5401990 (1995-03-01), Nakagawara
patent: 5488244 (1996-01-01), Quek et al.
patent: 5495441 (1996-02-01), Hong
patent: 5781031 (1998-07-01), Bertin et al.
patent: 6365942 (2002-04-01), Kocon et al.
patent: 6504204 (2003-01-01), Hsu et al.
patent: 5-102480 (1993-04-01), None
Ohara Masanori
Ueda Naoki
Nixon & Vanderhye P.C.
Rocchegiani Renzo N.
Sharp Kabushiki Kaisha
Smith Matthew
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