Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1997-10-02
2002-06-11
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S339000, C257S488000
Reexamination Certificate
active
06404025
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the structure and fabrication process of MOSFET power devices. More particularly, this invention relates to a novel and improved MOSFET device structure and fabrication process wherein reduced number of masks are employed such that MOSFET power devices can be manufactured with simplified method at lower cost while the device reliability is improved.
2. Description of the Prior Art
The goal of reducing the production cost of the MOSFET power device cannot be easily achieved. This is particularly true when the power MOSFET devices become more complicate both in cell structure and in device topology. It causes the fabrication processes to become more complex which typically requires application of increased number of masks. Longer manufacture time cycles are required which leads to higher production costs. Increased number of masks employed in the fabrication processes introduces further concerns. As more masks and processing steps are applied, more uncertainties of production yield and product reliability are introduced. The production costs are further impacted due to these undesirable factors. For these reasons, many technical improvements are attempted to reduce the number of masks employed for MOSFET fabrication.
In U.S. Pat. No. 5,404,040 entitled “Structure and Fabrication of Power MOSFETS including Termination Structures” (issued on Apr. 4, 1994), Hshieh etl al. disclose a power MOSFET, as that shown in FIG.
1
. The MOSFET is manufactured by a five mask process on a semiconductor body
2000
and
2001
. A first insulating layer
2002
lies over the active and termination areas. A main polysilicon portion,
2003
C and
2003
B, lies over the first insulating layer largely above the active area. Also a first and second peripheral polysilicon segments
2003
C
1
and
2003
C
2
lie over the first insulating layer above the termination area which are etched as two separated segments with a separating gap
2013
E. A gate electrode
2016
contacts the main polysilicon potion. A source electrode
2015
A and
2015
B, is formed to contact the active area, the termination area and the first polysilicon segment
2003
C
1
through an opening in the second insulating layer
2012
. The second polysilicon segment
2003
C
2
extends over a scribe line section of the termination area where the semiconductor is cut into separate dice. In this termination area, a metal portion is formed to contact this second polysilicon segment During a dicing process, the second polysilicon segment and the metal portion are electrically shorted to the semiconductor body. The metal portion in combination of the second polysilicon segment are useful to equalize the potential at the outer peripheral of the MOSFET and reduces the likelihood of device malfunction.
The MOSFET as that shown in
FIG. 1
presents several difficulties in the fabrication processes. Specifically, it is difficult to remove a silicon segment to form the gap
2013
E for separating the first polysilicon segment
2003
C
1
from the second polysilicon segment
2013
C
2
. If the gap
2013
E is a small gap, then a wet etch process is not suitable due to its difficulties in controlling the etching dimensions. On the other hand, if a dry etch is applied in order to make the gap
2013
E with a small gap-width, then the opening surface may be damaged as a result of dry etch process. In addition to the difficulties in manufacture, the structure in the termination area presents further difficulties and limitations. Due to the opening of this gap
2013
E, a passivation layer is required to prevent mobile ions from entering into the device. As will be further discussed below, a requirement of applying a pad mask to define the passivation layer is necessary which results in more complicate manufacture processes and higher MOSFET production cost Additionally, this configuration in the termination area causes a walk out phenomenon of the breakdown voltage. A more detail technical description will be provided below when a novel structural feature of this invention is disclosed to improve the termination configuration in order to resolve the walkout problems.
The number of masks required in DMOS fabrication generally is closely related to the structure of a MOSFET transistor, and particularly the requirement to apply a pad mask is related to its requirement to have a passivation layer. Please refer to
FIGS. 2A and 2B
respectively for a cross sectional view of a conventional planar and trenched device structure for a DMOS transistor
10
. The DMOS transistor
10
is supported on a N+ substrate
15
and an N− epi-taxial layer
20
formed on its top. The cell
10
includes a p-body region
25
surrounding a source region
30
wherein the source region
30
and the p-body region
25
formed in the substrate and partially covered under a gate
40
. The body-region
25
and the source region
30
are insulated from the gate
40
by a gate oxide layer
35
. The DMOS cell
10
is then covered with a PSG or BPSG protection layer
45
. A contact mask is then applied to open contact areas. The metal layer
50
is deposited on top of the device which is then etched by applying a metal mask to define the source metal
50
-
1
, the gate metal
50
-
2
, the field plate
50
-
3
and an equal protection ring (EQR)
50
-
4
. After defining the metal segments
50
-
1
to
50
-
4
, due to the requirement to prevent mobile ions from entering into the device between the gaps of these metal contacts, e.g., gap-A, gap-B, and gap-C as that shown in
FIG. 1
, a passivation layer typical comprising a PSG, a silicon nitride or an oxynitride layer has to be formed. The passivation layer
60
is then deposited and etched by the use of a pad mask to expose the areas above the source metal
50
-
1
and gate metal
50
-
2
. The gaps between the metal segments, i.e., gap-A, gap-B, and gap-C, are now covered by the passivation layer
60
. The metal ions are blocked by either the metal segments
50
-
1
to
50
-
4
, or by the passivation layer and prevented from entering into the device.
Disadvantages of the foregoing process is that it requires additional manufacture processes and time due to the application of a pad mask for removing the passivation layer
60
from the areas above the source metal
50
-
1
and the gate pad
50
-
2
. Furthermore, the passivation layer typically formed with PSG, silicon nitride, or oxynitride, having a thickness ranging from 0.5 to 1.5 micrometers. Under a very heavy contamination situation, the thickness of the passivation layer may not be sufficient to block the mobile ions from entering into the transistor cells. As these metal segments
50
-
1
to
50
-
4
are defined usually by employing a wet etching process, the gaps between the metal segments typically have a large lateral distance of approximately 15-20 micrometers because of the undercut. With such large gaps between the metal segments, the passivation layer in the gaps can only be formed in conformity with the layer profile and thus having the same thickness as the passivation layer deposited in other areas. The thickness of the passivation layer covering the gaps between the metal segments is thus mostly limited to be about the same as passivation layer formed else where. With a thickness limitation described above and the fact that the passivation layer cannot reliably protect the DMOS device from invasion of mobile ions, the reliability of a DMOS device cannot be assured. The traditional wet etching process typically performed for patterning the metal layer to produce large lateral gaps between the metal segments in a conventional DMOS device thus leads to this technical difficulty.
Therefore, there is still a need in the art of power device fabrication, particularly for DMOS design and fabrication, to provide a structure and fabrication process that would resolve these difficulties.
SUMMARY OF THE PRESENT INVENTION
It is therefore an object of the present invention to provide a new MOSFET f
Hshieh Fwu-Iuan
Tsui Yan Man
Hu Shouxiang
Lin Bo-In
Magepower Semiconductor Corp.
Thomas Tom
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