Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-08-05
2001-04-10
Lee, Eddie C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S249000, C257S329000, C257S333000, C257S335000, C257S409000, C257S488000, C257S487000, C257S491000, C257S508000, C438S159000, C438S197000, C438S267000, C438S299000, C438S454000
Reexamination Certificate
active
06215152
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to semiconductor field effect transistors and fabrication processes, and more particularly the invention relates to field effect transistors having gate-drain shields to reduce capacitative coupling. The invention has particular applicability to RF/microwave power MOSFET transistors including an extended drain MOSFET, vertical DMOS transistor, and lateral DMOS transistor.
The gate to drain feedback capacitance (Cgd or Crss) of any MOSFET device must be minimized in order to maximize RF gain and minimize signal distortion. The gate to drain feedback capacitance is critical since it is effectively multiplied by the voltage gain of the device or C
effective
=Crss (1+gm R
L
) where gm is the transconductance of the device and R
L
is the load resistance. The gate length must be minimized also to reduce transit time, increase transconductance, and reduce the on-resistance of the device.
Sub-micron narrow gate lithography can be used to enhance the characteristics of the MOSFET device, but fabrication of such device requires the use of very expensive wafer stepper systems.
Heretofore the use of a Faraday shield made of metal or polysilicon formed over the gate structure has been proposed as disclosed in U.S. Pat. No. 5,252,848. As shown in
FIG. 1
, a lateral DMOS transistor including an N+ source
10
, an N+ drain
12
, and an N− drain extended region
14
are separated by a P channel region
16
over which is formed a gate electrode
18
separated from the channel region
16
by gate oxide
20
. In accordance with the U.S. Pat. No. 5,252,848 patent, the source metal contact
22
extends over gate
18
and is isolated therefrom by an insulative layer
24
. The extended source metal
22
provides a Faraday shield between the gate
18
and the drain metal
26
thus reducing gate-drain capacitance. However, substantial gate-drain capacitance exists between gate
18
and the N− drain region
14
as illustrated at
28
.
Spectrian (Assignee of the present application) has introduced a buried shield LDMOS transistor as illustrated in
FIG. 2
in which gate-drain shielding is enhanced by providing a buried shield
30
which underlies gate
18
to reduce the capacitance
28
of FIG.
1
. Further, a buried shield metal
30
is placed on the surface of insulator
24
to reduce capacitance between gate
18
and drain metal
26
. However, the overlap of gate
18
over buried shield
30
results in higher input capacitance for the device.
Thus, there is a high cost of scaling down gate dimensions to try and minimize gate-drain capacitance. The described prior art devices using Faraday shields do not completely minimize the gate-drain capacitance, and prior art structures cannot be successfully applied to vertical DMOS devices. The overlap of the gate over the shield in the structure of
FIG. 2
results in a higher input capacitance.
SUMMARY OF THE INVENTION
In accordance with the present invention, a MOSFET has a buried shield plate under the gate and over the drain with the gate being formed on the periphery of the buried shield plate as a self-aligned structure with minimal or no overlap of the gate over the shield plate.
In fabricating the MOSFET in accordance with the invention, the buried shield is first defined and then gate material is deposited over the buried shield with a dielectric therebetween. Excess gate material is removed by anisotropic etching thereby leaving gate material around the periphery of the buried shield. A non-critical mask is then employed to protect the gate material on the source side over the channel, and then the exposed gate material is removed by etching. The resulting structure has minimal or no overlap of gate material over the buried shield.
The invention and objects and features thereof will be more readily apparent from the following detailed description and appended claims when taken with the drawing.
REFERENCES:
patent: 4455565 (1984-06-01), Goodman et al.
patent: 5067000 (1991-11-01), Eimori et al.
patent: 5367189 (1994-11-01), Nakamura
patent: 5430314 (1995-07-01), Yilmaz
patent: 5521419 (1996-05-01), Wkamiya et al.
patent: 5912490 (1999-06-01), Hebert et al.
patent: 5918137 (1999-06-01), Ng et al.
patent: 6001710 (1999-12-01), Francois et al.
Cree Inc.
Lee Eddie C.
Townsend and Townsend / and Crew LLP
Warren Matthew E.
Woodward Henry K.
LandOfFree
MOSFET having self-aligned gate and buried shield and method... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with MOSFET having self-aligned gate and buried shield and method..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and MOSFET having self-aligned gate and buried shield and method... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2435239