MOSFET having high and low dielectric materials

Details MOSFET having high and low dielectric materials MOSFET having high and low dielectric materials

1999-06-29

2004-04-20

Tran, Minhloan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S295000, C257S310000, C257S324000, C257S325000

Reexamination Certificate

active

06724025

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a MOS type semiconductor device used with LSI etc., especially, to a semiconductor device using high permittivity material or ferroelectric material as a gate insulation film.
In recent years, by scaling the transistor by the fine processing technology etc. in a semiconductor technological field, several 1,000,000 transistors come to be integrated in one high chip of several cm
2
, and are used here and there of a mainframe computer, a personal computer, home electric appliances product, a car, and a portable telephone, etc.
In general, when the transistor is reduced, for example, when the size of the transistor is made 1/k by scaling in a constant electric field, the parameter of each transistor is scaled as follows. Where, thickness of the gate oxide film: Tox/k, length of the channel: L/k, channel width: W/k, density of impurities in the Si substrate: NA×k, junction depth of the source-drain section: Xj/k, and power-supply voltage: Vdd/k.
Thus, the area of the transistor is reduced proportional to reciprocal of square like the following equation.
(
W/k
)×(
L/k
)=
WL/k
2
.
Moreover, a gate load capacity C of the transistor is shown in the following equation.
&AutoLeftMatch;
C
=
 
⁢
ϵ
/
(
Tox
/
k
)
×
(
W
/
k
)
/
(
L
/
k
)
=
 
⁢
{
(
ϵ
/
Tox
)
×
W
×
L
}
/
k
Then, driving current of the transistor is reduced to 1/k like the following equation.
I
=&mgr;∈/(
Tox/k
)×(
W/k
)/(
L/k
)×(
Vdd/k−Vt
)×
k
~{(&mgr;∈/
Tox
)×(
W/L
)×
Vdd−Vdd}/k.
Therefore, when the wiring capacity and the wiring resistance are disregarded, an operation delay t of the transistor is reduced like the following equation in proportion to the scaling coefficient k.
t=Q/I
={(
C/k
)×(
Vdd/k
)}/(
I/k
)=
t/k
Where, Q shows the charge.
It can be said that today's LSI can be sped up by scaling the transistor.
FIG. 1A
shows real size of the transistor which has been achieved in mass production today. This transistor has thickness of the gate oxide film of Tox=5 nm, channel length of L=0.2 &mgr;m, and junction depth of the source-drain section of Xj=100 nm.
By the way, it is expected that a big leakage current of the gate oxide film, which flows between the gate electrode and the substrate and between the gate electrode and the source-drain, becomes a trouble, when the transistor will be scaled hereafter toward a previous generation.
In a current gate oxide film, an FN-tunneling current (Fowler-Nordeim-Tunneling) is predominant. Here, the FN-tunneling current increases substantially by the second power of the electric field as the electric field applied to the gate oxide film becomes large by thinning the oxide film. In addition, the tunneling current (Direct-Tunneling) starts to flow directly from the vicinity of Tox=3 nm to 4 nm, when thinning the oxide film. It has a big problem where a greatly large gate current flows compared with the FN-tunneling, since the direct-tunneling current is not only increases in proportion to the electric field but also increases in exponential compared with thinning the gate oxide film.
A following fatal disadvantage is caused by the leakage current of the gate oxide film: 1) The standby leakage current of the entire LSI chip increases. 2) Since the charge accumulated in the gate leaks, a dynamic circuit is not operated. 3) Since the charge accumulated in the cell capacitor such as DRAM leaks, it is not operated as the memory. 4) It is impossible to compare with the turning on current of the transistor when thinning the gate oxide film, and a static circuit itself is not operated.
FIG. 1B
shows the size of the transistor after ten years when scaling of the transistor today continues. This transistor has thickness of the gate oxide film of Tox=1.5 nm, channel length of L=50 nm (0.05 &mgr;m), and junction depth of the source-drain section of Xj=10 nm.
The gate leakage current increases by the actual measurement as many as eight digits, e.g., from 4×10
−17
A/&mgr;m
2
to 4×10
−9
A/&mgr;m
2
at Vdd=0.5V, when the thickness of the gate oxide film is changed from Tox=3.5 nm to 1.6 nm. With this, the charge stored by the gate of the transistor of size of, for example, W/L=0.4 &mgr;m/0.05 &mgr;m and the Tox=1.5 nm is as follows.
0.4 &mgr;m×0.05 &mgr;m×8.854×10
−14
F/cm×4/1.5 nm=0.5 fF
On the other hand, the gate leakage current is as follows.
0.4 &mgr;m×0.05 &mgr;m×4×10
−9
A/&mgr;m
2
=8×10
−11
A
Therefore, since the time when the charge can be held is only
Q/I
=0.5 fF/(8×10
−11
A)=6 &mgr;s.
It cannot be used as the memory by all means, when the difference of one digit to two digits is considered, it is impossible to apply to a dynamic circuit. In addition, the leakage current of the entire LSI chip of 1 cm
2
square is,
4×10
−9
A/&mgr;m
2×10
4
&mgr;m×10
4
&mgr;m=0.4 A.
It becomes an extraordinarily large value as mentioned-above.
On the other hand, in a case of constructing the transistor of L=0.05 &mgr;m, by giving up thinning the gate oxide film and setting driving current of the transistor to not so large value, the short channel effect becomes large, thereby it becomes extremely difficult to suppress a DIBL (Drain Induced Barrier Lowering) and a deterioration in S factor. When channel length L is L=0.4{Xj×Tox(Ws+wd)
2
}
⅓
or less, the short channel effect usually starts to become remarkable. Where, Xj is junction depth of the source-drain section, Tox is a thickness of the gate oxide film, and Ws+Wd is a sum of the width of a depletion layer of the source and the drain. It is necessary to over-scale the junction depth Xj etc. of the source-drain section to a value corresponding to Tox which cannot be reduces.
However, since Xj is still small as about 100 nm today, a lot of difficulties are attended to form a more shallow junction. That is, since an FN-tunneling current and a direct tunneling current increase in exponential to keep using the oxide film to the conventional gate insulation film, there is a disadvantage with a lot of difficulties.
A try which uses the high dielectric film as the gate insulation film as shown in
FIG. 2
to solve this disadvantage film, recently. While relative permittivity (∈r) of the gate oxide film such as SiO
2
is about four, since the relative permittivity is big such that the relative permittivity is about 7 to 8 in Si
3
N
4
and NO, the relative permittivity is about 20 to 30 in Ta
2
O
5
, the relative permittivity is about 80 in TiO
2
, the relative permittivity is 100 to 200 in SrTiO
3
, the relative permittivity is 250 to 300 in Ba
X
Sr
1−x
TiO
3
, the same driving current of the transistor is:
I=&mgr;∈O∈r/Tox×
(
W/L
)×
Vdd×Vdd,
if the material having a large relative permittivity are used as a gate insulation film.
Therefore, the substantial gate insulation film thickness can be thickened to obtain the same driving current, that is, to obtain the gate capacity per the same unit area by conversion of the thickness of the oxide film. For example, in TiO
2
, it is possible to achieve conversion Tef=1.5 nm of the thickness of the oxide film by a thick film such as film thickness:
T
=(80/4)×1.5 nm=30 nm.
However, the following problems exist when the gate insulation film is achieved by the high dielectric film. Since the band gap of the insulation film generally becomes a small value such that material has the larger relative permittivity, as a result, the barrier heights between the gate electrode and the gate insulation film and between the Si substrate and the gate insulation film become small. The small barrier height means that it is easy for e

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