MOSFET device with low gate contact resistance

Details MOSFET device with low gate contact resistance MOSFET device with low gate contact resistance

2008-06-03

2008-06-03

Pham, Hoai v (Department: 2892)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S374000, C257SE27060

Reexamination Certificate

active

07382027

ABSTRACT:
A CMOS RF device and a method to fabricate said device with low gate contact resistance are described. Conventional MOS transistor is first formed with isolation regions, poly-silicon gate structure, sidewall spacers around poly gate, and implanted source/drain with lightly and heavily doped regions. A silicon dioxide layer such as TEOS is deposited, planarized with chemical mechanical polishing (CMP) to expose the gate and treated with dilute HF etchant to recess the silicon dioxide layer below the surface of the gate. Silicon nitride is then deposited and planarized with CMP and then etched except around the gates, using a oversize poly-silicon gate mask. Inter-level dielectric mask is then deposited, contact holes etched, and contact metal is deposited to form the transistor. During contact hole etch over poly-silicon gate, silicon nitride around the poly gate acts as an etch stop. Resulting structure with direct gate contact achieves significantly reduced gate resistance and thereby improved noise performance at high frequency operation, increased unit power gain frequency (fmax), and reduced gate delay.

REFERENCES:
patent: 5731239 (1998-03-01), Wong et al.
patent: 6010954 (2000-01-01), Ho et al.
patent: 6271087 (2001-08-01), Kinoshita et al.
patent: 6281059 (2001-08-01), Cheng et al.
patent: 6326651 (2001-12-01), Manabe

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