MOSFET device to reduce gate-width without increasing JFET resis

Details MOSFET device to reduce gate-width without increasing JFET resis MOSFET device to reduce gate-width without increasing JFET resis

1997-11-28

2000-04-11

Mintel, William

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257329, 257335, 257339, 257341, 438230, 438231, 438944, 438948, H01L 2976, H01L 2994, H01L 31062, H01L 31113, H01L 31119

Patent

active

060491043

ABSTRACT:
The present invention discloses a method for fabricating a MOSFET device supported on a substrate. The method includes the steps of (a) growing an oxide layer on the substrate followed by depositing a polysilicon layer and applying a gate mask for performing an undercutting dry etch for patterning a plurality of polysilicon gates with a gate width narrower than a width of the gate mask; (b) applying the gate mask as body implant blocking mask for implanting a body dopant followed by removing the gate mask and carrying out a body diffusion for forming body regions; (c) applying a source blocking mask for implanting a source dopant to form a plurality of source regions; (d) forming an overlying insulation layer covering the MOSFET device followed by applying a dry oxide etch with a contact mask as a second mask to open a plurality of contact openings there through then removing the contact mask; (e) performing a high temperature reflow process for the overlying insulation layer and for driving the source regions into designed junction depths; (f) depositing a metal layer followed by applying a metal mask for patterning the metal layer to define a plurality of metal segments.

REFERENCES:
patent: 5248627 (1993-09-01), Williams
patent: 5479037 (1995-12-01), Hshieh et al.
patent: 5545908 (1996-08-01), Tokura et al.
patent: 5731611 (1998-03-01), Hshieh et al.
patent: 5757046 (1998-05-01), Fujihira et al.
patent: 5844277 (1998-12-01), Hshieh et al.
patent: 5894150 (1999-04-01), Hshieh

Affiliated with

Also associated with

Rating

MOSFET device to reduce gate-width without increasing JFET resis does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with MOSFET device to reduce gate-width without increasing JFET resis, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and MOSFET device to reduce gate-width without increasing JFET resis will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1178550