MOSFET device having controlled parasitic isolation threshold vo

Details MOSFET device having controlled parasitic isolation threshold vo MOSFET device having controlled parasitic isolation threshold vo

1994-12-30

1997-07-22

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257374, 257394, 257407, 257510, 257754, 257763, H01L 2976

Patent

active

056506546

ABSTRACT:
A MOSFET has shallow trenches of a thick oxide for isolating the MOSFET device from a surrounding substrate. The MOSFET has a gate wiring layer that includes co-aligned metallurgy of a predetermined work function at regions where the gate wiring layer passes over the oxide of the isolation trenches. The co-aligned metallurgy of predetermined work function is operative to increase the parasitic threshold voltage associated with the MOSFET's parasitic leakage currents.

REFERENCES:
patent: 3602782 (1971-08-01), Klein
patent: 3608189 (1971-09-01), Gray
patent: 3798513 (1974-03-01), Ono
patent: 4599792 (1986-07-01), Cade et al.
patent: 4990983 (1991-02-01), Custode et al.
patent: 5061647 (1991-10-01), Roth et al.
patent: 5081066 (1992-01-01), Kim
patent: 5210435 (1993-05-01), Rothe et al.
patent: 5247198 (1993-09-01), Homma et al.
patent: 5268330 (1993-12-01), Givens et al.
patent: 5418179 (1995-05-01), Hotta
patent: 5514910 (1996-05-01), Koyama

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