Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
1999-08-24
2002-08-20
Loke, Steven (Department: 2811)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S270000, C438S306000
Reexamination Certificate
active
06436798
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a multiple T-shaped gate MOSFET device, and more particularly to a MOSFET device, which can increase the ICs' density and speed without physically scaling down the device's channel length and width.
2. Description of the Related Art
In the process of fabricating a MOSFET device, in order to scale down the device, both the channel width and length dimensions are shortened. As the attempt to increase the ULSI device density and speed continues, the technology in the deep sub-micron regime becomes more and more difficult so that it eventually may reach a theoretical limitation. As a result, it is impossible to limitlessly increase the device's density and speed. In addition, the short channel effect will render the technology even more prohibitive. For example, as the channel width and the length dimensions are shortened, punch through of the carriers and the hot carrier effect occur. When the device is even more scaled down, the short channel effect becomes especially significant.
FIGS. 1A
to
1
H are schematic, cross-sectional views of conventional MOSFET device formation processes. Referring to
FIG. 1A
, a device includes a substrate
100
, a pad oxide layer
102
, a silicon nitride layer
104
, and a photoresist layer
106
. A mask
108
is used to pattern the device. Referring to
FIG. 1B
, a trench
107
is formed in the substrate
100
by defining the photoresist layer
106
, the silicon nitride layer
104
, the pad oxide layer
102
and the substrate
100
.
The remainder of the photoresist layer
106
a
and the silicon nitride layer
104
a
are removed to expose the remainder of the pad oxide layer
102
a
, as shown in FIG.
1
C. Referring to
FIG. 1D
, a dielectric layer
110
is formed in the trench
107
and over the substrate
100
. The dielectric layer
110
is polished to expose the substrate
100
and form a shallow trench isolation (STI) structure
110
a
as shown in FIG.
1
E. Then, a gate oxide layer
112
, a metal layer
114
, and a photoresist layer
116
are formed on the substrate in turn. Next, a mask
118
is further used to pattern the device.
A gate
114
a
is formed on the substrate
100
by defining the photoresist layer
116
, the metal layer
114
, and the gate oxide layer
112
as shown in FIG.
1
F. Then, the substrate
100
is implanted with ions to form a shallow doped region
111
in the substrate
100
. Referring to
FIG. 1G
, an oxide layer
120
is deposited on the substrate
100
. Then, the oxide layer
120
is etched to form spacers
120
a
besides the gate
114
a
by dry etching as shown in FIG.
1
H. Then, the substrate
100
is implanted with ions to form a deep doped region
113
.
The technology will reach a limit in developing high integrity and operating rate. When the device becomes smaller the short channel effect becomes especially apparent.
The references regarding changing the gate shape to increase the integrity and the operating rate are:
1. F. E. Holmes and C. A. T Salama, Solid State Electron, 17.791 (1974) for V-shape MOS.
2. C. A. T Salama, Solid State Electron, 20.1003 (1977) for U-shape MOS.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide an improved resolution to the conventional MOSFET device. Using a multiple T-shaped gate (utilizing the trench technology), device density and speed can be increased without physically scaling down the MOSFET's channel length and width. Once this approach is adopted in the effort to miniature ULSI devices, the short channel effect will be of much less concern.
It is another object of the invention to provide a MOSFET with multiple T-shaped gate, wherein the gate length is increased to improve the operating rate and the integrity.
The invention achieves the above-identified objects by providing a new method of fabricating a MOSFET with a multiple T-shaped gate. The fabricating method includes the following steps. A substrate with an active region and a non-active region is provided. A plurality of trenches are formed in both the active region and the non-active regions in the substrate. An insulating layer is formed in the trenches. The insulating layer in the trenches of the active region is etched. A thin insulating layer is formed in the trenches of the active region and over the surface of the substrate. A conducting layer is formed in the trenches of the active region. The conducting layer is defined to form a gate. The device is implanted with first ions. Then, the device is further implanted with second ions by using a mask, wherein the mask expose the trenches of the active region, and the opening of the mask is wider than the trench.
The MOSFET device includes at least the following structures. A substrate includes an active region and a non-active region, wherein the active region includes a plurality of trenches and the non-active region includes a plurality of shallow trench isolation structures. A thin insulating layer is formed in the trenches of the active region and over the substrate. A multiple T-shaped gate is formed with a first part and a second part, wherein the first part is formed between two trenches on the substrate, and the second part is formed in the trenches of the active region. A source/drain region includes a shallow doped region and a deep doped region, wherein the shallow doped region is in the substrate under the first part, and the deep doped region is in the substrate beside the second part.
REFERENCES:
patent: 4835584 (1989-05-01), Lancaster
patent: 5142640 (1992-08-01), Iwamatsu
patent: 5329142 (1994-07-01), Kitagawa et al.
patent: 5763310 (1998-06-01), Gardner
patent: 5864158 (1999-01-01), Liu et al.
Hu Shouxiang
Loke Steven
United Microelectronics Corp.
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