MOSFET cell array

Details MOSFET cell array MOSFET cell array

1992-09-30

1994-11-15

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257398, 257519, 257648, 257774, 257775, 437 62, 437 63, 437 69, 437 72, 437235, 437978, H01L 2712, H01L 21302

Patent

active

053650824

ABSTRACT:
A CMOS memory cell array, and a process for making it, that avoids problems caused by LOCOS isolation of cells. Moats are formed by etching away columns of a thick field oxide layer. The moats have two-tiered sidewalls, such that an upper tier is sloped, and a lower tier is more vertical. This approach provides the advantages of sloped sidewalls, but avoids filament problems. After the moats are formed, subsequent fabrication steps may be in accordance with conventional fabrication techniques for CMOS arrays.

REFERENCES:
patent: 4502210 (1985-03-01), Okumura et al.
patent: 5023690 (1991-06-01), Verret et al.
patent: 5081517 (1992-01-01), Contiero et al.
patent: 5091768 (1992-02-01), Yamazaki
patent: 5160996 (1992-11-01), Odanaka

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