MOSFET-based electrostatic discharge (ESD) protection...

Details MOSFET-based electrostatic discharge (ESD) protection... MOSFET-based electrostatic discharge (ESD) protection...

2000-10-06

2002-06-18

Weiss, Howard (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

With means to control surface effects

With inversion-preventing shield electrode

Reexamination Certificate

active

06407445

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor device structures and, in particular, to electrostatic discharge protection structures for use with integrated circuits.
2. Description of the Related Art
Electrostatic discharge (ESD) protection devices are commonly employed in an integrated circuit (IC) to protect electronic devices in the IC from spurious pulses of excessive voltage (e.g., an ESD event, Human Body Model [HBM] event, or Electrical Overstress [EOS] event). See, for example, S.M. Sze,
Electrostatic Discharge Damage,
in VLSI Technology, Second Edition, 648-650 (McGraw Hill, 1988). A variety of conventional ESD protection devices that make extensive use of diodes, metal-oxide-semiconductor field effect transistors (MOSFETs), and bipolar transistors are known in the field. For example, conventional ESD protection devices for use with CMOS integrated circuits include Grounded-Gate MOS (GGMOS) ESD protection structures and Low Voltage Silicon Controlled Rectifier (LVSCR) ESD protection structures. Descriptions of these and other conventional ESD protection structures are available in Haigang, et al.,
A Comparison Study of ESD Protection for RFICs: Performance vs. Parasitics,
2000 IEEE Radio Frequency Integrated Circuits Symposium, 235-237 (2000); U.S. patent application for “MOSFET Structure For Use in ESD Protection Devices” (filed Jul. 17, 2000; application number not yet assigned) and U.S. patent application Ser. No. 09/205,110 (filed Dec. 3, 1998), each of which is hereby fully incorporated by reference.
Referring to
FIG. 1
, a representative conventional MOSFET-based ESD protection structure
10
for use with CMOS ICs is illustrated. The MOSFET-based ESD protection structure
10
includes a gate silicon dioxide (SiO
2
) layer
12
overlying a P-type silicon substrate
14
. Also present in the P-type silicon substrate
14
are N-type source region
16
and N-type drain region
18
. Channel region
20
is located in the P-type silicon substrate
14
and connects the N-type source region
16
to the N-type drain region
18
underneath the gate silicon dioxide layer
12
. A patterned polysilicon gate layer
22
overlies gate silicon dioxide layer
12
. Gate sidewall spacer
24
, typically of silicon dioxide or silicon nitride, is formed on lateral surfaces of the patterned polysilicon gate layer
22
and gate silicon dioxide layer
12
.
Conventional MOSFET-based ESD protection structure
10
also includes an interconnect dielectric layer
26
(typically a silicon dioxide [SiO
2
] based layer) overlying the P-type silicon substrate
14
, N-type source region
16
, gate sidewall spacer
24
, patterned polysilicon gate layer
22
and N-type drain region
18
. Substrate contact
28
, source region contact
30
, gate contact
32
and drain region contact
34
, each formed through interconnect dielectric layer
26
, are also present in conventional MOSFET-based ESD protection structure
10
. Substrate contact
28
, source region contact
30
, gate contact
32
and drain region contact
34
are typically formed of one or more metallic layers (e.g., aluminum, an aluminum alloy, titanium, and/or titanium-nitride). An electrical schematic illustrating conventional MOSFET-based ESD protection structure
10
of
FIG. 1
arranged in a basic conventional GGMOS ESD protection configuration is provided in FIG.
2
.
Conventional MOSFET structures are designed to exhibit breakdown characteristics only at voltages well above their standard operating supply voltage. However, during an ESD event, conventional MOSFET-based structures used in ESD protection devices exhibit significant current conduction via a parasitic lateral bipolar mechanism. For a further description of such current conduction in MOSFET-based structures via a parasitic lateral bipolar mechanism, see E. A. Amerasekera et al.,
ESD in Silicon Integrated Circuits
, sections 3.5.2 and 4.2.3. (John Wiley & Sons, 1995), which are hereby fully incorporated by reference.
A significant physical limitation of conventional MOSFET-based ESD protection structures is their susceptibility to thermal overheating and associated irreversible damage (e.g., local melting). As a consequence, conventional MOSFET-based ESD protection structures are unstable in the event that a critical temperature of approximately 1300° K is reached during an ESD event. Still needed in the field, therefore, is an ESD protection structure for use in MOS ICs that is relatively immune to thermal overheating and, thus, stable during an ESD event.
SUMMARY OF THE INVENTION
The present invention provides a MOSFET-based ESD protection structure for use in MOS ICs that is relatively immune to thermal overheating and, thus, stable during an ESD event. Immunity to thermal overheating and, thereby, stability during an ESD event are attained in the present invention by employing a floating heat sink to dissipate the heat generated during such an ESD event.
MOSFET-based ESD protection structures according to the present invention include a semiconductor substrate (e.g., a silicon substrate) of a first conductivity type (typically P-type) with a gate insulation layer (e.g., a gate silicon dioxide layer) thereon. The gate insulation layer underlies a patterned gate layer. Also included are a source region and drain region of a second conductivity type, each disposed in the semiconductor substrate, as well as a floating heat sink disposed above, and in contact with, the drain region. An interconnect dielectric layer is disposed over the semiconductor substrate, the source region, the patterned gate layer and the drain region.
The floating heat sink is formed of a material with a heat capacity and/or thermal conductivity that is greater than the heat capacity and/or thermal conductivity of the material (typically an SiO
2
-based material) which constitutes the interconnect dielectric layer. Therefore, the floating heat sink can be formed of metal (e.g., aluminum, and aluminum alloy, or copper) and/or polysilicon. The floating heat sink is disposed above, and in contact with, the drain region since this location is near (i.e., within approximately
2
microns, and preferably within 1.5 microns, of) the point of maximum temperature generation during a transitory ESD event (e.g., a 10 nano-second rising and 150 nano-second falling MIL standard HBM event). The electrically floating nature of the floating heat sink insures that the electrical behavior (e.g., I-V characteristics and transients) of the remainder of the MOSFET-based ESD protection structure is essentially unaltered by its presence.
MOSFET-based ESD protection structures according to the present invention can be thought of as a variant of an MOS snap-back ESD protection structure with the distinctive addition of a floating heat sink within 2 microns of the point of maximum temperature generation during a transitory ESD event. The floating heat sink provides immunity to overheating and, consequently, superior ESD protection performance.


REFERENCES:
patent: 5828120 (1998-10-01), Ishikawa

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